LXR uboot/board/barco/platinum/platinum.h

   1/*
   2 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#ifndef _PLATINUM_H_
   8#define _PLATINUM_H_
   9
  10#include <miiphy.h>
  11#include <asm/arch/crm_regs.h>
  12#include <asm/io.h>
  13
  14/* Defines */
  15
  16#define ECSPI1_PAD_CLK          (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
  17                                 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
  18                                 PAD_CTL_HYS)
  19#define ECSPI2_PAD_CLK          (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
  20                                 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  21                                 PAD_CTL_HYS)
  22#define ECSPI_PAD_MOSI          (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
  23                                 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
  24                                 PAD_CTL_HYS)
  25#define ECSPI_PAD_MISO          (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
  26                                 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
  27                                 PAD_CTL_HYS)
  28#define ECSPI_PAD_SS            (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \
  29                                 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
  30                                 PAD_CTL_HYS)
  31
  32#define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  33                                 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  34
  35#define I2C_PAD_CTRL            (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  36                                 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  37                                 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  38#define I2C_PAD_CTRL_SCL        (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  39                                 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
  40                                 PAD_CTL_ODE | PAD_CTL_SRE_SLOW)
  41
  42#define UART_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  43                                 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
  44                                 PAD_CTL_HYS)
  45
  46#define USDHC_PAD_CTRL          (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW | \
  47                                PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
  48                                PAD_CTL_HYS)
  49
  50
  51#define PC                      MUX_PAD_CTRL(I2C_PAD_CTRL)
  52#define PC_SCL                  MUX_PAD_CTRL(I2C_PAD_CTRL_SCL)
  53
  54/* Prototypes */
  55
  56int platinum_setup_enet(void);
  57int platinum_setup_i2c(void);
  58int platinum_setup_spi(void);
  59int platinum_setup_uart(void);
  60int platinum_phy_config(struct phy_device *phydev);
  61int platinum_init_gpio(void);
  62int platinum_init_usb(void);
  63int platinum_init_finished(void);
  64
  65static inline void ccgr_init(void)
  66{
  67        struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  68
  69        writel(0x00C03F3F, &ccm->CCGR0);
  70        writel(0x0030FC03, &ccm->CCGR1);
  71        writel(0x0FFFC000, &ccm->CCGR2);
  72        writel(0x3FF00000, &ccm->CCGR3);
  73        writel(0xFFFFF300, &ccm->CCGR4);        /* enable NAND/GPMI/BCH clks */
  74        writel(0x0F0000C3, &ccm->CCGR5);
  75        writel(0x000003FF, &ccm->CCGR6);
  76}
  77
  78static inline void gpr_init(void)
  79{
  80        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  81
  82        /* enable AXI cache for VDOA/VPU/IPU */
  83        writel(0xF00000CF, &iomux->gpr[4]);
  84        /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  85        writel(0x007F007F, &iomux->gpr[6]);
  86        writel(0x007F007F, &iomux->gpr[7]);
  87}
  88
  89#endif /* _PLATINUM_H_ */
  90