1/* 2 * Configuation settings for the Freescale MCF5475 board. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * board/config.h - configuration options, board specific 12 */ 13 14#ifndef _M5475EVB_H 15#define _M5475EVB_H 16 17/* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22#define CONFIG_DISPLAY_BOARDINFO 23 24#define CONFIG_MCFUART 25#define CONFIG_SYS_UART_PORT (0) 26#define CONFIG_BAUDRATE 115200 27 28#undef CONFIG_HW_WATCHDOG 29#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 30 31/* Command line configuration */ 32#undef CONFIG_CMD_DATE 33#define CONFIG_CMD_PCI 34#define CONFIG_CMD_REGINFO 35 36#define CONFIG_SLTTMR 37 38#define CONFIG_FSLDMAFEC 39#ifdef CONFIG_FSLDMAFEC 40# define CONFIG_MII 1 41# define CONFIG_MII_INIT 1 42# define CONFIG_HAS_ETH1 43 44# define CONFIG_SYS_DMA_USE_INTSRAM 1 45# define CONFIG_SYS_DISCOVER_PHY 46# define CONFIG_SYS_RX_ETH_BUFFER 32 47# define CONFIG_SYS_TX_ETH_BUFFER 48 48# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 49 50# define CONFIG_SYS_FEC0_PINMUX 0 51# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 52# define CONFIG_SYS_FEC1_PINMUX 0 53# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 54 55# define MCFFEC_TOUT_LOOP 50000 56/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 57# ifndef CONFIG_SYS_DISCOVER_PHY 58# define FECDUPLEX FULL 59# define FECSPEED _100BASET 60# else 61# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 62# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 63# endif 64# endif /* CONFIG_SYS_DISCOVER_PHY */ 65 66# define CONFIG_IPADDR 192.162.1.2 67# define CONFIG_NETMASK 255.255.255.0 68# define CONFIG_SERVERIP 192.162.1.1 69# define CONFIG_GATEWAYIP 192.162.1.1 70 71#endif 72 73#ifdef CONFIG_CMD_USB 74# define CONFIG_USB_OHCI_NEW 75# define CONFIG_USB_STORAGE 76 77# ifndef CONFIG_CMD_PCI 78# define CONFIG_CMD_PCI 79# endif 80# define CONFIG_PCI_OHCI 81# define CONFIG_DOS_PARTITION 82 83# undef CONFIG_SYS_USB_OHCI_BOARD_INIT 84# undef CONFIG_SYS_USB_OHCI_CPU_INIT 85# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 86# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" 87# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 88#endif 89 90/* I2C */ 91#define CONFIG_SYS_I2C 92#define CONFIG_SYS_I2C_FSL 93#define CONFIG_SYS_FSL_I2C_SPEED 80000 94#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 95#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 96#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 97 98/* PCI */ 99#ifdef CONFIG_CMD_PCI 100#define CONFIG_PCI 1 101#define CONFIG_PCI_PNP 1 102#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 103 104#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 105 106#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 107#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 108#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 109 110#define CONFIG_SYS_PCI_IO_BUS 0x71000000 111#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 112#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 113 114#define CONFIG_SYS_PCI_CFG_BUS 0x70000000 115#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 116#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 117#endif 118 119#define CONFIG_UDP_CHECKSUM 120 121#ifdef CONFIG_MCFFEC 122# define CONFIG_IPADDR 192.162.1.2 123# define CONFIG_NETMASK 255.255.255.0 124# define CONFIG_SERVERIP 192.162.1.1 125# define CONFIG_GATEWAYIP 192.162.1.1 126#endif /* FEC_ENET */ 127 128#define CONFIG_HOSTNAME M547xEVB 129#define CONFIG_EXTRA_ENV_SETTINGS \ 130 "netdev=eth0\0" \ 131 "loadaddr=10000\0" \ 132 "u-boot=u-boot.bin\0" \ 133 "load=tftp ${loadaddr) ${u-boot}\0" \ 134 "upd=run load; run prog\0" \ 135 "prog=prot off bank 1;" \ 136 "era ff800000 ff83ffff;" \ 137 "cp.b ${loadaddr} ff800000 ${filesize};"\ 138 "save\0" \ 139 "" 140 141#define CONFIG_PRAM 512 /* 512 KB */ 142#define CONFIG_SYS_LONGHELP /* undef to save memory */ 143 144#ifdef CONFIG_CMD_KGDB 145# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 146#else 147# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 148#endif 149 150#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 151#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 152#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 153#define CONFIG_SYS_LOAD_ADDR 0x00010000 154 155#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK 156#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 157 158#define CONFIG_SYS_MBAR 0xF0000000 159#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) 160#define CONFIG_SYS_INTSRAMSZ 0x8000 161 162/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ 163 164/* 165 * Low Level Configuration Settings 166 * (address mappings, register initial values, etc.) 167 * You should know what you are doing if you make changes here. 168 */ 169/*----------------------------------------------------------------------- 170 * Definitions for initial stack pointer and data area (in DPRAM) 171 */ 172#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 173#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 174#define CONFIG_SYS_INIT_RAM_CTRL 0x21 175#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) 176#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ 177#define CONFIG_SYS_INIT_RAM1_CTRL 0x21 178#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 179#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 180 181/*----------------------------------------------------------------------- 182 * Start addresses for the final memory configuration 183 * (Set up by the startup code) 184 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 185 */ 186#define CONFIG_SYS_SDRAM_BASE 0x00000000 187#define CONFIG_SYS_SDRAM_CFG1 0x73711630 188#define CONFIG_SYS_SDRAM_CFG2 0x46770000 189#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 190#define CONFIG_SYS_SDRAM_EMOD 0x40010000 191#define CONFIG_SYS_SDRAM_MODE 0x018D0000 192#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA 193#ifdef CONFIG_SYS_DRAMSZ1 194# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) 195#else 196# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ 197#endif 198 199#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 200#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 201 202#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 203#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 204 205#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 206 207/* Reserve 256 kB for malloc() */ 208#define CONFIG_SYS_MALLOC_LEN (256 << 10) 209/* 210 * For booting Linux, the board info and command line data 211 * have to be in the first 8 MB of memory, since this is 212 * the maximum mapped by the Linux kernel during initialization ?? 213 */ 214#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 215 216/*----------------------------------------------------------------------- 217 * FLASH organization 218 */ 219#define CONFIG_SYS_FLASH_CFI 220#ifdef CONFIG_SYS_FLASH_CFI 221# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 222# define CONFIG_FLASH_CFI_DRIVER 1 223# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 224# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 225# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 226# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 227#ifdef CONFIG_SYS_NOR1SZ 228# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 229# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) 230# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 231#else 232# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 233# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) 234#endif 235#endif 236 237/* Configuration for environment 238 * Environment is not embedded in u-boot but at offset 0x40000 on the flash. 239 * First time runing may have env crc error warning if there is 240 * no correct environment on the flash. 241 */ 242#define CONFIG_ENV_OFFSET 0x40000 243#define CONFIG_ENV_SECT_SIZE 0x10000 244#define CONFIG_ENV_IS_IN_FLASH 1 245 246/*----------------------------------------------------------------------- 247 * Cache Configuration 248 */ 249#define CONFIG_SYS_CACHELINE_SIZE 16 250 251#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 252 CONFIG_SYS_INIT_RAM_SIZE - 8) 253#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 254 CONFIG_SYS_INIT_RAM_SIZE - 4) 255#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ 256 CF_CACR_IDCM) 257#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 258#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 259 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 260 CF_ACR_EN | CF_ACR_SM_ALL) 261#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ 262 CF_CACR_IEC | CF_CACR_ICINVA) 263#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 264 CF_CACR_DEC | CF_CACR_DDCM_P | \ 265 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 266 267/*----------------------------------------------------------------------- 268 * Chipselect bank definitions 269 */ 270/* 271 * CS0 - NOR Flash 1, 2, 4, or 8MB 272 * CS1 - NOR Flash 273 * CS2 - Available 274 * CS3 - Available 275 * CS4 - Available 276 * CS5 - Available 277 */ 278#define CONFIG_SYS_CS0_BASE 0xFF800000 279#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) 280#define CONFIG_SYS_CS0_CTRL 0x00101980 281 282#ifdef CONFIG_SYS_NOR1SZ 283#define CONFIG_SYS_CS1_BASE 0xE0000000 284#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) 285#define CONFIG_SYS_CS1_CTRL 0x00101D80 286#endif 287 288#endif /* _M5475EVB_H */ 289