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19#ifndef __CONFIG_H
20#define __CONFIG_H
21
22
23
24
25#define CONFIG_440EPX 1
26#define CONFIG_440 1
27
28#ifndef CONFIG_SYS_TEXT_BASE
29#define CONFIG_SYS_TEXT_BASE 0xFFF90000
30#endif
31
32#define CONFIG_DISPLAY_BOARDINFO
33
34#define CONFIG_SYS_CLK_FREQ 33333400
35
36#if 0
37#define CONFIG_4xx_DCACHE
38#endif
39
40#define CONFIG_BOARD_EARLY_INIT_F 1
41#define CONFIG_MISC_INIT_F 1
42#define CONFIG_MISC_INIT_R 1
43#define CONFIG_BOARD_TYPES 1
44
45
46
47
48#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
49#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
50
51#define CONFIG_PRAM 0
52
53#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
54#define CONFIG_SYS_SDRAM_BASE 0x00000000
55#define CONFIG_SYS_FLASH_BASE 0xfc000000
56#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
57#define CONFIG_SYS_NAND_ADDR 0xd0000000
58#define CONFIG_SYS_OCM_BASE 0xe0010000
59#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
60#define CONFIG_SYS_PCI_BASE 0xe0000000
61#define CONFIG_SYS_PCI_MEMBASE 0x80000000
62#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
63#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
64#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
65#define CONFIG_SYS_PCI_MEMSIZE 0x80000000
66
67#define CONFIG_SYS_USB2D0_BASE 0xe0000100
68#define CONFIG_SYS_USB_DEVICE 0xe0000000
69#define CONFIG_SYS_USB_HOST 0xe0000400
70#define CONFIG_SYS_FPGA_BASE0 0xef000000
71#define CONFIG_SYS_FPGA_BASE1 0xef100000
72#define CONFIG_SYS_RESET_BASE 0xef200000
73
74
75
76
77
78#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
79#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
80#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
81#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
82
83
84
85
86#define CONFIG_CONS_INDEX 1
87#define CONFIG_SYS_NS16550_SERIAL
88#define CONFIG_SYS_NS16550_REG_SIZE 1
89#define CONFIG_SYS_NS16550_CLK get_serial_clock()
90#undef CONFIG_SYS_EXT_SERIAL_CLOCK
91#define CONFIG_BAUDRATE 115200
92
93#define CONFIG_SYS_BAUDRATE_TABLE \
94 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
95
96
97
98
99#define CONFIG_ENV_IS_IN_EEPROM 1
100
101
102
103
104#define CONFIG_RTC_RX8025
105
106
107
108
109#define CONFIG_SYS_FLASH_CFI
110#define CONFIG_FLASH_CFI_DRIVER
111
112#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
113
114#define CONFIG_SYS_MAX_FLASH_BANKS 1
115#define CONFIG_SYS_MAX_FLASH_SECT 512
116
117#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
118#define CONFIG_SYS_FLASH_WRITE_TOUT 500
119
120#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
121#define CONFIG_SYS_FLASH_PROTECTION 1
122
123#define CONFIG_SYS_FLASH_EMPTY_INFO
124#define CONFIG_SYS_FLASH_QUIET_TEST 1
125
126#ifdef CONFIG_ENV_IS_IN_FLASH
127#define CONFIG_ENV_SECT_SIZE 0x20000
128#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
129#define CONFIG_ENV_SIZE 0x2000
130
131
132#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
133#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
134#endif
135
136#ifdef CONFIG_ENV_IS_IN_EEPROM
137#define CONFIG_I2C_ENV_EEPROM_BUS 0
138#define CONFIG_ENV_OFFSET 0
139#define CONFIG_ENV_SIZE 0x1000
140#endif
141
142
143
144
145#define CONFIG_DDR_DATA_EYE
146#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
147
148
149
150
151
152#define CONFIG_SYS_I2C
153#define CONFIG_SYS_I2C_PPC4XX
154#define CONFIG_SYS_I2C_PPC4XX_CH0
155#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
156#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
157#define CONFIG_SYS_I2C_PPC4XX_CH1
158#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000
159#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
160
161#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
162#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
163#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
164#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
165#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
166
167#define CONFIG_SYS_EEPROM_WREN 1
168#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
169
170
171
172
173
174#define CONFIG_DTT_SENSORS { 0, 1 }
175
176
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181
182
183
184
185
186
187#define CONFIG_DTT_ADM1021
188#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
189
190#define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \
191 "\\\"painit\\\" to preboot command"
192
193#undef CONFIG_BOOTARGS
194
195
196#define CONFIG_HOSTNAME pmc440
197#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0"
198#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
199
200#define CONFIG_EXTRA_ENV_SETTINGS \
201 CONFIG_SYS_BOOTFILE \
202 CONFIG_SYS_ROOTPATH \
203 "fdt_file=/tftpboot/pmc440/pmc440.dtb\0" \
204 "netdev=eth0\0" \
205 "ethrotate=no\0" \
206 "nfsargs=setenv bootargs root=/dev/nfs rw " \
207 "nfsroot=${serverip}:${rootpath}\0" \
208 "ramargs=setenv bootargs root=/dev/ram rw\0" \
209 "addip=setenv bootargs ${bootargs} " \
210 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
211 ":${hostname}:${netdev}:off panic=1\0" \
212 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
213 "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \
214 "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
215 "nand_boot_fdt=run nandargs addip addtty addmisc;" \
216 "bootm ${kernel_addr} - ${fdt_addr}\0" \
217 "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \
218 "tftp ${fdt_addr_r} ${fdt_file};" \
219 "run nfsargs addip addtty addmisc;" \
220 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
221 "kernel_addr=ffc00000\0" \
222 "kernel_addr_r=200000\0" \
223 "fpga_addr=fff00000\0" \
224 "fdt_addr=fff80000\0" \
225 "fdt_addr_r=800000\0" \
226 "fpga=fpga loadb 0 ${fpga_addr}\0" \
227 "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \
228 "update=protect off fff90000 ffffffff;era fff90000 ffffffff;" \
229 "cp.b 200000 fff90000 70000\0" \
230 ""
231
232
233#define CONFIG_LOADS_ECHO 1
234#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
235
236#define CONFIG_PPC4xx_EMAC
237#define CONFIG_IBM_EMAC4_V4 1
238#define CONFIG_MII 1
239#define CONFIG_PHY_ADDR 0
240
241#define CONFIG_PHY_GIGE 1
242
243#define CONFIG_HAS_ETH0
244#define CONFIG_SYS_RX_ETH_BUFFER 32
245
246#define CONFIG_HAS_ETH1 1
247#define CONFIG_PHY1_ADDR 1
248#define CONFIG_RESET_PHY_R 1
249
250
251#define CONFIG_USB_OHCI_NEW
252#define CONFIG_USB_STORAGE
253#define CONFIG_SYS_OHCI_BE_CONTROLLER
254
255#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
256#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
257#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
258#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
259#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
260
261
262#define USB_2_0_DEVICE
263
264
265#define CONFIG_MAC_PARTITION
266#define CONFIG_DOS_PARTITION
267#define CONFIG_ISO_PARTITION
268
269#define CONFIG_CMD_BSP
270#define CONFIG_CMD_DATE
271#define CONFIG_CMD_DTT
272#define CONFIG_CMD_EEPROM
273#define CONFIG_CMD_NAND
274#define CONFIG_CMD_PCI
275#define CONFIG_CMD_REGINFO
276
277
278#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
279 CONFIG_SYS_POST_CPU | \
280 CONFIG_SYS_POST_UART | \
281 CONFIG_SYS_POST_I2C | \
282 CONFIG_SYS_POST_CACHE | \
283 CONFIG_SYS_POST_FPU | \
284 CONFIG_SYS_POST_ETHER | \
285 CONFIG_SYS_POST_SPR)
286
287#define CONFIG_LOGBUFFER
288#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000
289
290#define CONFIG_SYS_CONSOLE_IS_IN_ENV
291
292#define CONFIG_SUPPORT_VFAT
293
294
295
296
297#define CONFIG_SYS_LONGHELP
298#if defined(CONFIG_CMD_KGDB)
299#define CONFIG_SYS_CBSIZE 1024
300#else
301#define CONFIG_SYS_CBSIZE 256
302#endif
303#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
304#define CONFIG_SYS_MAXARGS 16
305#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
306
307#define CONFIG_SYS_MEMTEST_START 0x0400000
308#define CONFIG_SYS_MEMTEST_END 0x0C00000
309
310#define CONFIG_SYS_LOAD_ADDR 0x100000
311#define CONFIG_SYS_EXTBDINFO 1
312
313#define CONFIG_CMDLINE_EDITING 1
314#define CONFIG_MX_CYCLIC 1
315#define CONFIG_VERSION_VARIABLE 1
316
317
318
319
320
321#define CONFIG_PCI
322#define CONFIG_PCI_INDIRECT_BRIDGE
323#define CONFIG_PCI_PNP
324#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0
325#define CONFIG_PCI_SCAN_SHOW
326#define CONFIG_SYS_PCI_TARGBASE 0x80000000
327
328
329#define CONFIG_SYS_PCI_TARGET_INIT
330#define CONFIG_SYS_PCI_MASTER_INIT
331#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
332
333#define CONFIG_PCI_BOOTDELAY 0
334
335
336#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
337#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441
338#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440
339
340#define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
341#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
342#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
343
344
345
346
347
348
349#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
350
351
352
353
354#define CONFIG_FPGA
355#define CONFIG_FPGA_XILINX
356#define CONFIG_FPGA_SPARTAN2
357#define CONFIG_FPGA_SPARTAN3
358
359#define CONFIG_FPGA_COUNT 2
360
361
362
363
364
365
366
367#define CONFIG_SYS_NAND_CS 2
368
369
370#define CONFIG_SYS_EBC_PB0AP 0x03017200
371#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
372
373
374#define CONFIG_SYS_EBC_PB2AP 0x018003c0
375#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
376
377
378#define CONFIG_SYS_EBC_PB1AP 0x7f817200
379#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
380
381
382#define CONFIG_SYS_EBC_PB4AP 0x03840f40
383#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_FPGA_BASE0 | 0x1c000)
384
385
386#define CONFIG_SYS_EBC_PB5AP 0x03840f40
387#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_FPGA_BASE1 | 0x1a000)
388
389
390
391
392#define CONFIG_SYS_MAX_NAND_DEVICE 1
393#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
394#define CONFIG_SYS_NAND_SELECT_DEVICE 1
395
396#if defined(CONFIG_CMD_KGDB)
397#define CONFIG_KGDB_BAUDRATE 230400
398#endif
399
400#define CONFIG_API 1
401
402#endif
403