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5#ifndef __CONFIG_BF537_STAMP_H__
6#define __CONFIG_BF537_STAMP_H__
7
8#include <asm/config-pre.h>
9
10
11
12
13#define CONFIG_BFIN_CPU bf537-0.2
14#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
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21
22#define CONFIG_CLKIN_HZ 25000000
23
24
25#define CONFIG_CLKIN_HALF 0
26
27
28#define CONFIG_PLL_BYPASS 0
29
30
31#define CONFIG_VCO_MULT 20
32
33
34#define CONFIG_CCLK_DIV 1
35
36
37#define CONFIG_SCLK_DIV 4
38
39
40
41
42#define CONFIG_MEM_ADD_WDTH 10
43#define CONFIG_MEM_SIZE 64
44
45#define CONFIG_EBIU_SDRRC_VAL 0x306
46#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
47
48#define CONFIG_EBIU_AMGCTL_VAL 0xFF
49#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
50#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
51
52#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
53#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
54
55
56
57
58#ifndef __ADSPBF534__
59#define ADI_CMDS_NETWORK 1
60#define CONFIG_BFIN_MAC
61#define CONFIG_NETCONSOLE 1
62#endif
63#define CONFIG_HOSTNAME bf537-stamp
64
65
66
67
68#define CONFIG_FLASH_CFI_DRIVER
69#define CONFIG_SYS_FLASH_BASE 0x20000000
70#define CONFIG_SYS_FLASH_CFI
71#define CONFIG_SYS_FLASH_PROTECTION
72#define CONFIG_SYS_MAX_FLASH_BANKS 1
73
74#define CONFIG_SYS_MAX_FLASH_SECT 71
75
76
77
78
79#define CONFIG_BFIN_SPI
80#define CONFIG_ENV_SPI_MAX_HZ 30000000
81#define CONFIG_SF_DEFAULT_SPEED 30000000
82#define CONFIG_SPI_FLASH_ALL
83
84
85
86
87#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
88#define CONFIG_ENV_IS_IN_SPI_FLASH
89#define CONFIG_ENV_OFFSET 0x10000
90#define CONFIG_ENV_SIZE 0x2000
91#define CONFIG_ENV_SECT_SIZE 0x10000
92#else
93#define CONFIG_ENV_IS_IN_FLASH
94#define CONFIG_ENV_OFFSET 0x4000
95#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
96#define CONFIG_ENV_SIZE 0x2000
97#define CONFIG_ENV_SECT_SIZE 0x2000
98#endif
99#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
100#define ENV_IS_EMBEDDED
101#else
102#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
103#endif
104#ifdef ENV_IS_EMBEDDED
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106
107
108
109
110# define LDS_BOARD_TEXT \
111 arch/blackfin/lib/built-in.o (.text*); \
112 arch/blackfin/cpu/built-in.o (.text*); \
113 . = DEFINED(env_offset) ? env_offset : .; \
114 common/env_embedded.o (.text*);
115#endif
116
117
118
119
120#define CONFIG_SYS_I2C
121#define CONFIG_SYS_I2C_ADI
122
123
124
125
126#define CONFIG_MMC_SPI
127#ifdef CONFIG_MMC_SPI
128#define CONFIG_MMC
129#define CONFIG_GENERIC_MMC
130#endif
131
132
133
134
135
136#ifdef CONFIG_NAND_PLAT
137#define CONFIG_SYS_NAND_BASE 0x20212000
138#define CONFIG_SYS_MAX_NAND_DEVICE 1
139
140#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
141#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
142#define BFIN_NAND_WRITE(addr, cmd) \
143 do { \
144 bfin_write8(addr, cmd); \
145 SSYNC(); \
146 } while (0)
147
148#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
149#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
150#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
151#endif
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178
179#if defined(CONFIG_BFIN_CF_IDE) || \
180 defined(CONFIG_BFIN_HDD_IDE) || \
181 defined(CONFIG_BFIN_TRUE_IDE)
182# define CONFIG_BFIN_IDE 1
183# define CONFIG_CMD_IDE
184#endif
185
186#if defined(CONFIG_BFIN_IDE)
187
188#define CONFIG_DOS_PARTITION 1
189
190
191
192#undef CONFIG_IDE_8xx_DIRECT
193#undef CONFIG_IDE_LED
194#undef CONFIG_IDE_RESET
195
196#define CONFIG_SYS_IDE_MAXBUS 1
197#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
198
199#undef CONFIG_EBIU_AMBCTL1_VAL
200#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
201
202#define CONFIG_CF_ATASEL_DIS 0x20311800
203#define CONFIG_CF_ATASEL_ENA 0x20311802
204
205#if defined(CONFIG_BFIN_TRUE_IDE)
206
207
208
209
210#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
211#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
212#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020
213#define CONFIG_SYS_ATA_REG_OFFSET 0x0020
214#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C
215#define CONFIG_SYS_ATA_STRIDE 2
216
217#elif defined(CONFIG_BFIN_CF_IDE)
218#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
219#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
220#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
221#define CONFIG_SYS_ATA_REG_OFFSET 0x0000
222#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E
223#define CONFIG_SYS_ATA_STRIDE 1
224
225#elif defined(CONFIG_BFIN_HDD_IDE)
226#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
227#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
228#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020
229#define CONFIG_SYS_ATA_REG_OFFSET 0x0020
230#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C
231#define CONFIG_SYS_ATA_STRIDE 2
232#undef CONFIG_SCLK_DIV
233#define CONFIG_SCLK_DIV 8
234#endif
235
236#endif
237
238
239
240
241#define CONFIG_MISC_INIT_R
242#define CONFIG_RTC_BFIN
243#define CONFIG_UART_CONSOLE 0
244
245
246#undef CONFIG_POST
247#ifdef CONFIG_POST
248#define CONFIG_SYS_POST_HOTKEYS_GPIO GPIO_PF5
249#define CONFIG_POST_BSPEC1_GPIO_LEDS \
250 GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
251#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
252 GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
253#define CONFIG_POST_BSPEC2_GPIO_NAMES \
254 10, 11, 12, 13,
255#define CONFIG_SYS_POST_FLASH_START 11
256#define CONFIG_SYS_POST_FLASH_END 71
257#endif
258
259
260#if 0
261#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
262#endif
263
264
265
266
267#include <configs/bfin_adi_common.h>
268
269#endif
270