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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1
12#define CONFIG_DLVISION 1
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16
17
18
19#define CONFIG_HOSTNAME dlvision
20#define CONFIG_IDENT_STRING " dlvision 0.02"
21#include "amcc-common.h"
22
23#define CONFIG_BOARD_EARLY_INIT_F
24#define CONFIG_MISC_INIT_R
25
26#define CONFIG_SYS_CLK_FREQ 33333333
27
28
29
30
31#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
32#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
33
34
35#define CONFIG_FIT_DISABLE_SHA256
36
37#define CONFIG_ENV_IS_IN_FLASH
38
39
40
41
42#define CONFIG_EXTRA_ENV_SETTINGS \
43 CONFIG_AMCC_DEF_ENV \
44 CONFIG_AMCC_DEF_ENV_POWERPC \
45 CONFIG_AMCC_DEF_ENV_NOR_UPD \
46 "kernel_addr=fc000000\0" \
47 "fdt_addr=fc1e0000\0" \
48 "ramdisk_addr=fc200000\0" \
49 ""
50
51#define CONFIG_PHY_ADDR 4
52#define CONFIG_HAS_ETH0
53#define CONFIG_HAS_ETH1
54#define CONFIG_PHY1_ADDR 0xc
55#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
56
57
58
59
60#define CONFIG_CMD_DTT
61#undef CONFIG_CMD_DIAG
62#undef CONFIG_CMD_EEPROM
63#undef CONFIG_CMD_IRQ
64
65
66
67
68#define CONFIG_SDRAM_BANK0 1
69
70
71#define CONFIG_SYS_SDRAM_CL 3
72#define CONFIG_SYS_SDRAM_tRP 20
73#define CONFIG_SYS_SDRAM_tRC 66
74#define CONFIG_SYS_SDRAM_tRCD 20
75#define CONFIG_SYS_SDRAM_tRFC 66
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83
84
85
86#define CONFIG_CONS_INDEX 1
87#undef CONFIG_SYS_EXT_SERIAL_CLOCK
88#undef CONFIG_SYS_405_UART_ERRATA_59
89#define CONFIG_SYS_BASE_BAUD 691200
90
91
92
93
94#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
95
96
97
98
99#define CONFIG_SYS_FLASH_CFI
100#define CONFIG_FLASH_CFI_DRIVER
101
102#define CONFIG_SYS_FLASH_BASE 0xFC000000
103#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
104
105#define CONFIG_SYS_MAX_FLASH_BANKS 1
106#define CONFIG_SYS_MAX_FLASH_SECT 512
107
108#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
109#define CONFIG_SYS_FLASH_WRITE_TOUT 500
110
111#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
112
113#define CONFIG_SYS_FLASH_EMPTY_INFO
114#define CONFIG_SYS_FLASH_QUIET_TEST 1
115
116#ifdef CONFIG_ENV_IS_IN_FLASH
117#define CONFIG_ENV_SECT_SIZE 0x20000
118#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
119#define CONFIG_ENV_SIZE 0x2000
120
121
122#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
123#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
124#endif
125
126
127
128
129#define CONFIG_SYS_4xx_GPIO_TABLE { \
130{ \
131 \
132{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
133{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
134{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
135{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
136{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
137{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
138{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
139{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
140{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
141{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
142{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
143{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
144{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
145{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
146{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
147{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
148{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
149{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
150{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
151{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
152{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
153{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
154{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
155{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
156{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
157{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
158{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
159{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
160{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
161{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
162{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
163{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
164} \
165}
166
167
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169
170
171#define CONFIG_SYS_TEMP_STACK_OCM 1
172
173
174#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
175#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
176#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
177#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
178
179#define CONFIG_SYS_GBL_DATA_OFFSET \
180 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
181#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
182
183
184
185
186
187
188#define CONFIG_SYS_EBC_PB0AP 0x92015480
189
190#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
191
192
193#define CONFIG_SYS_EBC_PB1AP 0x92015480
194
195#define CONFIG_SYS_EBC_PB1CR 0xFB858000
196
197
198#define CONFIG_UART_BASE 0x7f100000
199#define CONFIG_SYS_EBC_PB2AP 0x92015480
200
201#define CONFIG_SYS_EBC_PB2CR 0x7f118000
202
203
204#define CONFIG_SYS_LATCH_BASE 0x7f200000
205#define CONFIG_SYS_EBC_PB3AP 0x92015480
206
207#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
208
209#endif
210