1/* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef __LS2_SIMU_H 8#define __LS2_SIMU_H 9 10#include "ls2080a_common.h" 11 12#define CONFIG_IDENT_STRING " LS2080A-SIMU" 13 14#define CONFIG_SYS_CLK_FREQ 100000000 15#define CONFIG_DDR_CLK_FREQ 133333333 16 17#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 18#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 19 20#define CONFIG_DIMM_SLOTS_PER_CTLR 1 21#define CONFIG_CHIP_SELECTS_PER_CTRL 4 22#ifdef CONFIG_SYS_FSL_HAS_DP_DDR 23#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 24#endif 25 26/* SMSC 91C111 ethernet configuration */ 27#define CONFIG_SMC91111 28#define CONFIG_SMC91111_BASE (0x2210000) 29 30#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 31#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 32 33#ifndef CONFIG_SYS_NO_FLASH 34#define CONFIG_FLASH_CFI_DRIVER 35#define CONFIG_SYS_FLASH_CFI 36#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 37#define CONFIG_SYS_FLASH_QUIET_TEST 38#endif 39 40/* 41 * NOR Flash Timing Params 42 */ 43#define CONFIG_SYS_NOR0_CSPR \ 44 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 45 CSPR_PORT_SIZE_16 | \ 46 CSPR_MSEL_NOR | \ 47 CSPR_V) 48#define CONFIG_SYS_NOR0_CSPR_EARLY \ 49 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 50 CSPR_PORT_SIZE_16 | \ 51 CSPR_MSEL_NOR | \ 52 CSPR_V) 53#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 54#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 55 FTIM0_NOR_TEADC(0x1) | \ 56 FTIM0_NOR_TEAHC(0x1)) 57#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 58 FTIM1_NOR_TRAD_NOR(0x1)) 59#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 60 FTIM2_NOR_TCH(0x0) | \ 61 FTIM2_NOR_TWP(0x1)) 62#define CONFIG_SYS_NOR_FTIM3 0x04000000 63#define CONFIG_SYS_IFC_CCR 0x01000000 64 65#ifndef CONFIG_SYS_NO_FLASH 66#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 67 68#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 69#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 70#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 71#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 72 73#define CONFIG_SYS_FLASH_EMPTY_INFO 74#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 75#endif 76 77#define CONFIG_NAND_FSL_IFC 78#define CONFIG_SYS_NAND_MAX_ECCPOS 256 79#define CONFIG_SYS_NAND_MAX_OOBFREE 2 80 81#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 82#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 83 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 84 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 85 | CSPR_V) 86#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 87 88#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 89 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 90 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 91 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 92 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 93 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 94 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 95 96#define CONFIG_SYS_NAND_ONFI_DETECTION 97 98/* ONFI NAND Flash mode0 Timing Params */ 99#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 100 FTIM0_NAND_TWP(0x18) | \ 101 FTIM0_NAND_TWCHT(0x07) | \ 102 FTIM0_NAND_TWH(0x0a)) 103#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 104 FTIM1_NAND_TWBE(0x39) | \ 105 FTIM1_NAND_TRR(0x0e) | \ 106 FTIM1_NAND_TRP(0x18)) 107#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 108 FTIM2_NAND_TREH(0x0a) | \ 109 FTIM2_NAND_TWHRE(0x1e)) 110#define CONFIG_SYS_NAND_FTIM3 0x0 111 112#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 113#define CONFIG_SYS_MAX_NAND_DEVICE 1 114#define CONFIG_MTD_NAND_VERIFY_WRITE 115#define CONFIG_CMD_NAND 116 117#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 118 119#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 120#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 121#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 122#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 123#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 124#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 125#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 126#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 127#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 128#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 129#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 130#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 131#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 132#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 133#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 134#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 135#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 136 137/* MMC */ 138#define CONFIG_MMC 139#ifdef CONFIG_MMC 140#define CONFIG_FSL_ESDHC 141#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 142#define CONFIG_GENERIC_MMC 143#define CONFIG_DOS_PARTITION 144#endif 145 146/* Debug Server firmware */ 147#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 148#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL 149 150/* MC firmware */ 151#define CONFIG_SYS_LS_MC_FW_IN_NOR 152#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL 153 154#define CONFIG_SYS_LS_MC_DPL_IN_NOR 155#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL 156 157#define CONFIG_SYS_LS_MC_DPC_IN_NOR 158#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL 159 160#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 161 162/* Store environment at top of flash */ 163#define CONFIG_ENV_IS_NOWHERE 1 164#define CONFIG_ENV_SIZE 0x1000 165 166#endif /* __LS2_SIMU_H */ 167