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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1
12#define CONFIG_NEO 1
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16
17
18
19#define CONFIG_HOSTNAME neo
20#define CONFIG_IDENT_STRING " neo 0.02"
21#include "amcc-common.h"
22
23#define CONFIG_BOARD_EARLY_INIT_F
24#define CONFIG_BOARD_EARLY_INIT_R
25#define CONFIG_MISC_INIT_R
26#define CONFIG_LAST_STAGE_INIT
27
28#define CONFIG_SYS_CLK_FREQ 33333333
29
30
31
32
33#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
34#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
35
36
37#define CONFIG_FIT_DISABLE_SHA256
38
39#define CONFIG_ENV_IS_IN_FLASH
40
41
42
43
44#define CONFIG_EXTRA_ENV_SETTINGS \
45 CONFIG_AMCC_DEF_ENV \
46 CONFIG_AMCC_DEF_ENV_POWERPC \
47 CONFIG_AMCC_DEF_ENV_NOR_UPD \
48 "kernel_addr=fc000000\0" \
49 "fdt_addr=fc1e0000\0" \
50 "ramdisk_addr=fc200000\0" \
51 ""
52
53#define CONFIG_PHY_ADDR 4
54#define CONFIG_HAS_ETH0
55#define CONFIG_HAS_ETH1
56#define CONFIG_PHY1_ADDR 0xc
57#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
58
59
60
61
62#define CONFIG_CMD_DTT
63#undef CONFIG_CMD_DIAG
64#undef CONFIG_CMD_EEPROM
65#undef CONFIG_CMD_IRQ
66
67
68
69
70#define CONFIG_SDRAM_BANK0 1
71
72
73#define CONFIG_SYS_SDRAM_CL 3
74#define CONFIG_SYS_SDRAM_tRP 20
75#define CONFIG_SYS_SDRAM_tRC 66
76#define CONFIG_SYS_SDRAM_tRCD 20
77#define CONFIG_SYS_SDRAM_tRFC 66
78
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85
86
87
88#define CONFIG_CONS_INDEX 1
89#define CONFIG_SYS_NS16550_SERIAL
90#define CONFIG_SYS_NS16550_REG_SIZE 1
91#define CONFIG_SYS_NS16550_CLK get_serial_clock()
92
93#undef CONFIG_SYS_EXT_SERIAL_CLOCK
94#undef CONFIG_SYS_405_UART_ERRATA_59
95#define CONFIG_SYS_BASE_BAUD 691200
96
97
98
99
100#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
101
102
103#define CONFIG_RTC_DS1337
104#define CONFIG_SYS_I2C_RTC_ADDR 0x68
105
106
107#define CONFIG_DTT_LM63 1
108#define CONFIG_DTT_SENSORS { 0 }
109#define CONFIG_DTT_PWM_LOOKUPTABLE \
110 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
111#define CONFIG_DTT_TACH_LIMIT 0xa10
112
113
114
115
116#define CONFIG_SYS_FLASH_CFI
117#define CONFIG_FLASH_CFI_DRIVER
118
119#define CONFIG_SYS_FLASH_BASE 0xFC000000
120#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
121
122#define CONFIG_SYS_MAX_FLASH_BANKS 1
123#define CONFIG_SYS_MAX_FLASH_SECT 512
124
125#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
126#define CONFIG_SYS_FLASH_WRITE_TOUT 500
127
128#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
129
130#define CONFIG_SYS_FLASH_EMPTY_INFO
131#define CONFIG_SYS_FLASH_QUIET_TEST 1
132
133#ifdef CONFIG_ENV_IS_IN_FLASH
134#define CONFIG_ENV_SECT_SIZE 0x20000
135#define CONFIG_ENV_ADDR 0xFFF00000
136#define CONFIG_ENV_SIZE 0x20000
137
138
139#define CONFIG_ENV_ADDR_REDUND 0xFFF20000
140#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
141#endif
142
143
144
145
146#define CONFIG_SYS_4xx_GPIO_TABLE { \
147{ \
148 \
149{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
150{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
151{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
152{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
153{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
154{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
155{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
156{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
157{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
158{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
159{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
160{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
161{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
162{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
163{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
164{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
165{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
166{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
167{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
168{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
169{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
170{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
171{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
172{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
173{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
174{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
175{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
176{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
177{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
178{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
179{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
180{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
181} \
182}
183
184
185
186
187
188#define CONFIG_SYS_TEMP_STACK_OCM 1
189
190
191#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
192#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
193#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
194#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
195
196#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
197#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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201
202
203
204#define CONFIG_SYS_EBC_PB0AP 0x92015480
205#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
206
207
208#define CONFIG_SYS_EBC_PB1AP 0x92015480
209#define CONFIG_SYS_EBC_PB1CR 0xFB85A000
210
211
212#define CONFIG_SYS_FPGA0_BASE 0x7f100000
213#define CONFIG_SYS_EBC_PB2AP 0x92015480
214#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
215
216#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
217
218#define CONFIG_SYS_FPGA_COUNT 1
219
220#define CONFIG_SYS_FPGA_PTR \
221 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
222
223#define CONFIG_SYS_FPGA_COMMON
224
225
226#define CONFIG_SYS_LATCH_BASE 0x7f200000
227#define CONFIG_SYS_EBC_PB3AP 0x92015480
228#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
229
230#define CONFIG_SYS_LATCH0_RESET 0xffff
231#define CONFIG_SYS_LATCH0_BOOT 0xffff
232#define CONFIG_SYS_LATCH1_RESET 0xffbf
233#define CONFIG_SYS_LATCH1_BOOT 0xffff
234
235#endif
236