1/* 2 * Configuation settings for the Renesas Solutions r0p7734 board 3 * 4 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __R0P7734_H 10#define __R0P7734_H 11 12#undef DEBUG 13#define CONFIG_CPU_SH7734 1 14#define CONFIG_R0P7734 1 15#define CONFIG_400MHZ_MODE 1 16/* #define CONFIG_533MHZ_MODE 1 */ 17 18#define CONFIG_BOARD_LATE_INIT 19#define CONFIG_SYS_TEXT_BASE 0x8FFC0000 20 21#define CONFIG_CMD_SDRAM 22#define CONFIG_CMD_ENV 23 24#define CONFIG_BAUDRATE 115200 25#define CONFIG_BOOTARGS "console=ttySC3,115200" 26 27#define CONFIG_VERSION_VARIABLE 28#undef CONFIG_SHOW_BOOT_PROGRESS 29 30/* Ether */ 31#define CONFIG_SH_ETHER 1 32#define CONFIG_SH_ETHER_USE_PORT (0) 33#define CONFIG_SH_ETHER_PHY_ADDR (0x0) 34#define CONFIG_PHYLIB 35#define CONFIG_PHY_SMSC 1 36#define CONFIG_BITBANGMII 37#define CONFIG_BITBANGMII_MULTI 38#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */ 39#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 40#ifndef CONFIG_SH_ETHER 41# define CONFIG_SMC911X 42# define CONFIG_SMC911X_16_BIT 43# define CONFIG_SMC911X_BASE (0x84000000) 44#endif 45 46/* I2C */ 47#define CONFIG_SH_SH7734_I2C 1 48#define CONFIG_HARD_I2C 1 49#define CONFIG_I2C_MULTI_BUS 1 50#define CONFIG_SYS_MAX_I2C_BUS 2 51#define CONFIG_SYS_I2C_MODULE 0 52#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 53#define CONFIG_SYS_I2C_SLAVE 0x50 54#define CONFIG_SH_I2C_DATA_HIGH 4 55#define CONFIG_SH_I2C_DATA_LOW 5 56#define CONFIG_SH_I2C_CLOCK 500000000 57#define CONFIG_SH_I2C_BASE0 0xFFC70000 58#define CONFIG_SH_I2C_BASE1 0xFFC7100 59 60/* undef to save memory */ 61#define CONFIG_SYS_LONGHELP 62/* Monitor Command Prompt */ 63/* Buffer size for input from the Console */ 64#define CONFIG_SYS_CBSIZE 256 65/* Buffer size for Console output */ 66#define CONFIG_SYS_PBSIZE 256 67/* max args accepted for monitor commands */ 68#define CONFIG_SYS_MAXARGS 16 69/* Buffer size for Boot Arguments passed to kernel */ 70#define CONFIG_SYS_BARGSIZE 512 71/* List of legal baudrate settings for this board */ 72#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 73 74/* SCIF */ 75#define CONFIG_SCIF_CONSOLE 1 76#define CONFIG_SCIF 1 77#define CONFIG_CONS_SCIF3 1 78 79/* Suppress display of console information at boot */ 80#undef CONFIG_SYS_CONSOLE_INFO_QUIET 81#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 82#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 83 84/* SDRAM */ 85#define CONFIG_SYS_SDRAM_BASE (0x88000000) 86#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) 87#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 88 89#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 90#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024) 91/* Enable alternate, more extensive, memory test */ 92#undef CONFIG_SYS_ALT_MEMTEST 93/* Scratch address used by the alternate memory test */ 94#undef CONFIG_SYS_MEMTEST_SCRATCH 95 96/* Enable temporary baudrate change while serial download */ 97#undef CONFIG_SYS_LOADS_BAUD_CHANGE 98 99/* FLASH */ 100#define CONFIG_FLASH_CFI_DRIVER 1 101#define CONFIG_SYS_FLASH_CFI 102#undef CONFIG_SYS_FLASH_QUIET_TEST 103#define CONFIG_SYS_FLASH_EMPTY_INFO 104#define CONFIG_SYS_FLASH_BASE (0xA0000000) 105#define CONFIG_SYS_MAX_FLASH_SECT 512 106 107/* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 108#define CONFIG_SYS_MAX_FLASH_BANKS 1 109#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 110 111/* Timeout for Flash erase operations (in ms) */ 112#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 113/* Timeout for Flash write operations (in ms) */ 114#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 115/* Timeout for Flash set sector lock bit operations (in ms) */ 116#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 117/* Timeout for Flash clear lock bit operations (in ms) */ 118#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 119 120/* 121 * Use hardware flash sectors protection instead 122 * of U-Boot software protection 123 */ 124#undef CONFIG_SYS_FLASH_PROTECTION 125#undef CONFIG_SYS_DIRECT_FLASH_TFTP 126 127/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 128#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 129/* Monitor size */ 130#define CONFIG_SYS_MONITOR_LEN (256 * 1024) 131/* Size of DRAM reserved for malloc() use */ 132#define CONFIG_SYS_MALLOC_LEN (256 * 1024) 133#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 134 135/* ENV setting */ 136#define CONFIG_ENV_IS_IN_FLASH 137#define CONFIG_ENV_OVERWRITE 1 138#define CONFIG_ENV_SECT_SIZE (128 * 1024) 139#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 140#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 141/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 142#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 143#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 144 145/* Board Clock */ 146#if defined(CONFIG_400MHZ_MODE) 147#define CONFIG_SYS_CLK_FREQ 50000000 148#else 149#define CONFIG_SYS_CLK_FREQ 44444444 150#endif 151#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 152#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 153#define CONFIG_SYS_TMU_CLK_DIV 4 154 155#endif /* __R0P7734_H */ 156