1/* 2 * Copyright (C) 2015, Savoir-faire Linux Inc. 3 * 4 * Derived from MX51EVK code by 5 * Guennadi Liakhovetski <lg@denx.de> 6 * Freescale Semiconductor, Inc. 7 * 8 * Configuration settings for the TS4800 Board 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13#ifndef __CONFIG_H 14#define __CONFIG_H 15 16/* High Level Configuration Options */ 17#define CONFIG_MX51 18 19#define CONFIG_DISPLAY_CPUINFO 20#define CONFIG_DISPLAY_BOARDINFO 21 22#define CONFIG_SYS_NO_FLASH /* No NOR Flash */ 23#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */ 24 25#define CONFIG_HW_WATCHDOG 26 27#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX 28 29/* text base address used when linking */ 30#define CONFIG_SYS_TEXT_BASE 0x90008000 31 32#include <asm/arch/imx-regs.h> 33 34/* enable passing of ATAGs */ 35#define CONFIG_CMDLINE_TAG 36#define CONFIG_SETUP_MEMORY_TAGS 37#define CONFIG_INITRD_TAG 38#define CONFIG_REVISION_TAG 39 40/* 41 * Size of malloc() pool 42 */ 43#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 44 45/* 46 * Hardware drivers 47 */ 48 49#define CONFIG_MXC_UART 50#define CONFIG_MXC_UART_BASE UART1_BASE 51#define CONFIG_MXC_GPIO 52 53/* 54 * SPI Configs 55 * */ 56#define CONFIG_HARD_SPI /* puts SPI: ready */ 57#define CONFIG_MXC_SPI /* driver for the SPI controllers*/ 58 59/* 60 * MMC Configs 61 * */ 62#define CONFIG_FSL_ESDHC 63#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR 64 65#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 66 67#define CONFIG_MMC 68 69#define CONFIG_GENERIC_MMC 70#define CONFIG_DOS_PARTITION 71 72/* 73 * Eth Configs 74 */ 75#define CONFIG_MII 76#define CONFIG_PHYLIB 77#define CONFIG_PHY_SMSC 78 79#define CONFIG_FEC_MXC 80#define IMX_FEC_BASE FEC_BASE_ADDR 81#define CONFIG_ETHPRIME "FEC" 82#define CONFIG_FEC_MXC_PHYADDR 0 83 84/* allow to overwrite serial and ethaddr */ 85#define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */ 86#define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */ 87#define CONFIG_BAUDRATE 115200 88 89/*********************************************************** 90 * Command definition 91 ***********************************************************/ 92 93/* Environment variables */ 94 95 96#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */ 97 98#define CONFIG_EXTRA_ENV_SETTINGS \ 99 "script=boot.scr\0" \ 100 "image=zImage\0" \ 101 "fdt_file=imx51-ts4800.dtb\0" \ 102 "fdt_addr=0x90fe0000\0" \ 103 "mmcdev=0\0" \ 104 "mmcpart=2\0" \ 105 "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ 106 "mmcargs=setenv bootargs root=${mmcroot}\0" \ 107 "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \ 108 "loadbootscript=" \ 109 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 110 "bootscript=echo Running bootscript from mmc ...; " \ 111 "source\0" \ 112 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \ 113 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 114 "mmcboot=echo Booting from mmc ...; " \ 115 "run mmcargs addtty; " \ 116 "if run loadfdt; then " \ 117 "bootz ${loadaddr} - ${fdt_addr}; " \ 118 "else " \ 119 "echo ERR: cannot load FDT; " \ 120 "fi; " 121 122 123#define CONFIG_BOOTCOMMAND \ 124 "mmc dev ${mmcdev}; if mmc rescan; then " \ 125 "if run loadbootscript; then " \ 126 "run bootscript; " \ 127 "else " \ 128 "if run loadimage; then " \ 129 "run mmcboot; " \ 130 "fi; " \ 131 "fi; " \ 132 "fi; " 133 134/* 135 * Miscellaneous configurable options 136 */ 137#define CONFIG_SYS_LONGHELP /* undef to save memory */ 138#define CONFIG_AUTO_COMPLETE 139#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 140/* Print Buffer Size */ 141#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 142#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 143#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 144 145#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 146 147#define CONFIG_CMDLINE_EDITING 148 149/*----------------------------------------------------------------------- 150 * Physical Memory Map 151 */ 152#define CONFIG_NR_DRAM_BANKS 1 153#define PHYS_SDRAM_1 CSD0_BASE_ADDR 154#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) 155 156#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) 157#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) 158#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) 159 160#define CONFIG_BOARD_EARLY_INIT_F 161 162#define CONFIG_SYS_INIT_SP_OFFSET \ 163 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 164#define CONFIG_SYS_INIT_SP_ADDR \ 165 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 166 167/* Low level init */ 168#define CONFIG_SYS_DDR_CLKSEL 0 169#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 170#define CONFIG_SYS_MAIN_PWR_ON 171 172/*----------------------------------------------------------------------- 173 * Environment organization 174 */ 175 176#define CONFIG_ENV_OFFSET (6 * 64 * 1024) 177#define CONFIG_ENV_SIZE (8 * 1024) 178#define CONFIG_ENV_IS_IN_MMC 179#define CONFIG_SYS_MMC_ENV_DEV 0 180 181#endif 182