LXR uboot/arch/arm/cpu/arm926ejs/spear/start.S

   1/*
   2 *  armboot - Startup Code for ARM926EJS CPU-core
   3 *
   4 *  Copyright (c) 2003  Texas Instruments
   5 *
   6 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
   7 *
   8 *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   9 *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
  10 *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
  11 *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12 *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
  13 *
  14 * SPDX-License-Identifier:     GPL-2.0+
  15 */
  16
  17
  18#include <config.h>
  19
  20/*
  21 *************************************************************************
  22 *
  23 * Startup Code (reset vector)
  24 *
  25 * Below are the critical initializations already taken place in BootROM.
  26 * So, these are not taken care in Xloader
  27 * 1. Relocation to RAM
  28 * 2. Initializing stacks
  29 *
  30 *************************************************************************
  31 */
  32
  33        .globl  reset
  34
  35reset:
  36/*
  37 * Xloader has to return back to BootROM in a few cases.
  38 * eg. Ethernet boot, UART boot, USB boot
  39 * Saving registers for returning back
  40 */
  41        stmdb   sp!, {r0-r12,r14}
  42        bl      cpu_init_crit
  43/*
  44 * Clearing bss area is not done in Xloader.
  45 * BSS area lies in the DDR location which is not yet initialized
  46 * bss is assumed to be uninitialized.
  47 */
  48        ldmia   sp!, {r0-r12,pc}
  49
  50/*
  51 *************************************************************************
  52 *
  53 * CPU_init_critical registers
  54 *
  55 * setup important registers
  56 * setup memory timing
  57 *
  58 *************************************************************************
  59 */
  60cpu_init_crit:
  61        /*
  62         * flush v4 I/D caches
  63         */
  64        mov     r0, #0
  65        mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
  66        mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
  67
  68        /*
  69         * enable instruction cache
  70         */
  71        mrc     p15, 0, r0, c1, c0, 0
  72        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
  73        mcr     p15, 0, r0, c1, c0, 0
  74
  75        /*
  76         * Go setup Memory and board specific bits prior to relocation.
  77         */
  78        stmdb   sp!, {lr}
  79        bl      _main   /* _main will call board_init_f */
  80        ldmia   sp!, {pc}
  81