LXR uboot/arch/powerpc/cpu/ppc4xx/usb

   1/*
   2 * URB OHCI HCD (Host Controller Driver) for USB.
   3 *
   4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
   6 *
   7 * usb-ohci.h
   8 */
   9
  10static int cc_to_error[16] = {
  11
  12/* mapping of the OHCI CC status to error codes */
  13        /* No  Error  */ 0,
  14        /* CRC Error  */ USB_ST_CRC_ERR,
  15        /* Bit Stuff  */ USB_ST_BIT_ERR,
  16        /* Data Togg  */ USB_ST_CRC_ERR,
  17        /* Stall      */ USB_ST_STALLED,
  18        /* DevNotResp */ -1,
  19        /* PIDCheck   */ USB_ST_BIT_ERR,
  20        /* UnExpPID   */ USB_ST_BIT_ERR,
  21        /* DataOver   */ USB_ST_BUF_ERR,
  22        /* DataUnder  */ USB_ST_BUF_ERR,
  23        /* reservd    */ -1,
  24        /* reservd    */ -1,
  25        /* BufferOver */ USB_ST_BUF_ERR,
  26        /* BuffUnder  */ USB_ST_BUF_ERR,
  27        /* Not Access */ -1,
  28        /* Not Access */ -1
  29};
  30
  31/* ED States */
  32
  33#define ED_NEW          0x00
  34#define ED_UNLINK       0x01
  35#define ED_OPER         0x02
  36#define ED_DEL          0x04
  37#define ED_URB_DEL      0x08
  38
  39/* usb_ohci_ed */
  40struct ed {
  41        __u32 hwINFO;
  42        __u32 hwTailP;
  43        __u32 hwHeadP;
  44        __u32 hwNextED;
  45
  46        struct ed *ed_prev;
  47        __u8 int_period;
  48        __u8 int_branch;
  49        __u8 int_load;
  50        __u8 int_interval;
  51        __u8 state;
  52        __u8 type;
  53        __u16 last_iso;
  54        struct ed *ed_rm_list;
  55
  56        struct usb_device *usb_dev;
  57        __u32 unused[3];
  58} __attribute__((aligned(16)));
  59typedef struct ed ed_t;
  60
  61/* TD info field */
  62#define TD_CC       0xf0000000
  63#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
  64#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
  65#define TD_EC       0x0C000000
  66#define TD_T        0x03000000
  67#define TD_T_DATA0  0x02000000
  68#define TD_T_DATA1  0x03000000
  69#define TD_T_TOGGLE 0x00000000
  70#define TD_R        0x00040000
  71#define TD_DI       0x00E00000
  72#define TD_DI_SET(X) (((X) & 0x07)<< 21)
  73#define TD_DP       0x00180000
  74#define TD_DP_SETUP 0x00000000
  75#define TD_DP_IN    0x00100000
  76#define TD_DP_OUT   0x00080000
  77
  78#define TD_ISO      0x00010000
  79#define TD_DEL      0x00020000
  80
  81/* CC Codes */
  82#define TD_CC_NOERROR      0x00
  83#define TD_CC_CRC          0x01
  84#define TD_CC_BITSTUFFING  0x02
  85#define TD_CC_DATATOGGLEM  0x03
  86#define TD_CC_STALL        0x04
  87#define TD_DEVNOTRESP      0x05
  88#define TD_PIDCHECKFAIL    0x06
  89#define TD_UNEXPECTEDPID   0x07
  90#define TD_DATAOVERRUN     0x08
  91#define TD_DATAUNDERRUN    0x09
  92#define TD_BUFFEROVERRUN   0x0C
  93#define TD_BUFFERUNDERRUN  0x0D
  94#define TD_NOTACCESSED     0x0F
  95
  96#define MAXPSW 1
  97
  98struct td {
  99        __u32 hwINFO;
 100        __u32 hwCBP;            /* Current Buffer Pointer */
 101        __u32 hwNextTD;         /* Next TD Pointer */
 102        __u32 hwBE;             /* Memory Buffer End Pointer */
 103
 104        __u16 hwPSW[MAXPSW];
 105        __u8 unused;
 106        __u8 index;
 107        struct ed *ed;
 108        struct td *next_dl_td;
 109        struct usb_device *usb_dev;
 110        int transfer_len;
 111        __u32 data;
 112
 113        __u32 unused2[2];
 114} __attribute__((aligned(32)));
 115typedef struct td td_t;
 116
 117#define OHCI_ED_SKIP    (1 << 14)
 118
 119/*
 120 * The HCCA (Host Controller Communications Area) is a 256 byte
 121 * structure defined in the OHCI spec. that the host controller is
 122 * told the base address of.  It must be 256-byte aligned.
 123 */
 124
 125#define NUM_INTS 32             /* part of the OHCI standard */
 126struct ohci_hcca {
 127        __u32 int_table[NUM_INTS];      /* Interrupt ED table */
 128#if defined(CONFIG_MPC5200)
 129        __u16 pad1;             /* set to 0 on each frame_no change */
 130        __u16 frame_no;         /* current frame number */
 131#else
 132        __u16 frame_no;         /* current frame number */
 133        __u16 pad1;             /* set to 0 on each frame_no change */
 134#endif
 135        __u32 done_head;        /* info returned for an interrupt */
 136        u8 reserved_for_hc[116];
 137} __attribute__((aligned(256)));
 138
 139/*
 140 * Maximum number of root hub ports.
 141 */
 142#define MAX_ROOT_PORTS  15      /* maximum OHCI root hub ports */
 143
 144/*
 145 * This is the structure of the OHCI controller's memory mapped I/O
 146 * region.  This is Memory Mapped I/O.  You must use the readl() and
 147 * writel() macros defined in asm/io.h to access these!!
 148 */
 149struct ohci_regs {
 150        /* control and status registers */
 151        __u32 revision;
 152        __u32 control;
 153        __u32 cmdstatus;
 154        __u32 intrstatus;
 155        __u32 intrenable;
 156        __u32 intrdisable;
 157        /* memory pointers */
 158        __u32 hcca;
 159        __u32 ed_periodcurrent;
 160        __u32 ed_controlhead;
 161        __u32 ed_controlcurrent;
 162        __u32 ed_bulkhead;
 163        __u32 ed_bulkcurrent;
 164        __u32 donehead;
 165        /* frame counters */
 166        __u32 fminterval;
 167        __u32 fmremaining;
 168        __u32 fmnumber;
 169        __u32 periodicstart;
 170        __u32 lsthresh;
 171        /* Root hub ports */
 172        struct ohci_roothub_regs {
 173                __u32 a;
 174                __u32 b;
 175                __u32 status;
 176                __u32 portstatus[MAX_ROOT_PORTS];
 177        } roothub;
 178} __attribute__((aligned(32)));
 179
 180/* OHCI CONTROL AND STATUS REGISTER MASKS */
 181
 182/*
 183 * HcControl (control) register masks
 184 */
 185#define OHCI_CTRL_CBSR  (3 << 0)        /* control/bulk service ratio */
 186#define OHCI_CTRL_PLE   (1 << 2)        /* periodic list enable */
 187#define OHCI_CTRL_IE    (1 << 3)        /* isochronous enable */
 188#define OHCI_CTRL_CLE   (1 << 4)        /* control list enable */
 189#define OHCI_CTRL_BLE   (1 << 5)        /* bulk list enable */
 190#define OHCI_CTRL_HCFS  (3 << 6)        /* host controller functional state */
 191#define OHCI_CTRL_IR    (1 << 8)        /* interrupt routing */
 192#define OHCI_CTRL_RWC   (1 << 9)        /* remote wakeup connected */
 193#define OHCI_CTRL_RWE   (1 << 10)       /* remote wakeup enable */
 194
 195/* pre-shifted values for HCFS */
 196#       define OHCI_USB_RESET   (0 << 6)
 197#       define OHCI_USB_RESUME  (1 << 6)
 198#       define OHCI_USB_OPER    (2 << 6)
 199#       define OHCI_USB_SUSPEND (3 << 6)
 200
 201/*
 202 * HcCommandStatus (cmdstatus) register masks
 203 */
 204#define OHCI_HCR        (1 << 0)        /* host controller reset */
 205#define OHCI_CLF        (1 << 1)        /* control list filled */
 206#define OHCI_BLF        (1 << 2)        /* bulk list filled */
 207#define OHCI_OCR        (1 << 3)        /* ownership change request */
 208#define OHCI_SOC        (3 << 16)       /* scheduling overrun count */
 209
 210/*
 211 * masks used with interrupt registers:
 212 * HcInterruptStatus (intrstatus)
 213 * HcInterruptEnable (intrenable)
 214 * HcInterruptDisable (intrdisable)
 215 */
 216#define OHCI_INTR_SO    (1 << 0)        /* scheduling overrun */
 217#define OHCI_INTR_WDH   (1 << 1)        /* writeback of done_head */
 218#define OHCI_INTR_SF    (1 << 2)        /* start frame */
 219#define OHCI_INTR_RD    (1 << 3)        /* resume detect */
 220#define OHCI_INTR_UE    (1 << 4)        /* unrecoverable error */
 221#define OHCI_INTR_FNO   (1 << 5)        /* frame number overflow */
 222#define OHCI_INTR_RHSC  (1 << 6)        /* root hub status change */
 223#define OHCI_INTR_OC    (1 << 30)       /* ownership change */
 224#define OHCI_INTR_MIE   (1 << 31)       /* master interrupt enable */
 225
 226/* Virtual Root HUB */
 227struct virt_root_hub {
 228        int devnum;             /* Address of Root Hub endpoint */
 229        void *dev;              /* was urb */
 230        void *int_addr;
 231        int send;
 232        int interval;
 233};
 234
 235/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
 236
 237/* destination of request */
 238#define RH_INTERFACE               0x01
 239#define RH_ENDPOINT                0x02
 240#define RH_OTHER                   0x03
 241
 242#define RH_CLASS                   0x20
 243#define RH_VENDOR                  0x40
 244
 245/* Requests: bRequest << 8 | bmRequestType */
 246#define RH_GET_STATUS           0x0080
 247#define RH_CLEAR_FEATURE        0x0100
 248#define RH_SET_FEATURE          0x0300
 249#define RH_SET_ADDRESS          0x0500
 250#define RH_GET_DESCRIPTOR       0x0680
 251#define RH_SET_DESCRIPTOR       0x0700
 252#define RH_GET_CONFIGURATION    0x0880
 253#define RH_SET_CONFIGURATION    0x0900
 254#define RH_GET_STATE            0x0280
 255#define RH_GET_INTERFACE        0x0A80
 256#define RH_SET_INTERFACE        0x0B00
 257#define RH_SYNC_FRAME           0x0C80
 258/* Our Vendor Specific Request */
 259#define RH_SET_EP               0x2000
 260
 261/* Hub port features */
 262#define RH_PORT_CONNECTION         0x00
 263#define RH_PORT_ENABLE             0x01
 264#define RH_PORT_SUSPEND            0x02
 265#define RH_PORT_OVER_CURRENT       0x03
 266#define RH_PORT_RESET              0x04
 267#define RH_PORT_POWER              0x08
 268#define RH_PORT_LOW_SPEED          0x09
 269
 270#define RH_C_PORT_CONNECTION       0x10
 271#define RH_C_PORT_ENABLE           0x11
 272#define RH_C_PORT_SUSPEND          0x12
 273#define RH_C_PORT_OVER_CURRENT     0x13
 274#define RH_C_PORT_RESET            0x14
 275
 276/* Hub features */
 277#define RH_C_HUB_LOCAL_POWER       0x00
 278#define RH_C_HUB_OVER_CURRENT      0x01
 279
 280#define RH_DEVICE_REMOTE_WAKEUP    0x00
 281#define RH_ENDPOINT_STALL          0x01
 282
 283#define RH_ACK                     0x01
 284#define RH_REQ_ERR                 -1
 285#define RH_NACK                    0x00
 286
 287/* OHCI ROOT HUB REGISTER MASKS */
 288
 289/* roothub.portstatus [i] bits */
 290#define RH_PS_CCS            0x00000001 /* current connect status */
 291#define RH_PS_PES            0x00000002 /* port enable status */
 292#define RH_PS_PSS            0x00000004 /* port suspend status */
 293#define RH_PS_POCI           0x00000008 /* port over current indicator */
 294#define RH_PS_PRS            0x00000010 /* port reset status */
 295#define RH_PS_PPS            0x00000100 /* port power status */
 296#define RH_PS_LSDA           0x00000200 /* low speed device attached */
 297#define RH_PS_CSC            0x00010000 /* connect status change */
 298#define RH_PS_PESC           0x00020000 /* port enable status change */
 299#define RH_PS_PSSC           0x00040000 /* port suspend status change */
 300#define RH_PS_OCIC           0x00080000 /* over current indicator change */
 301#define RH_PS_PRSC           0x00100000 /* port reset status change */
 302
 303/* roothub.status bits */
 304#define RH_HS_LPS            0x00000001 /* local power status */
 305#define RH_HS_OCI            0x00000002 /* over current indicator */
 306#define RH_HS_DRWE           0x00008000 /* device remote wakeup enable */
 307#define RH_HS_LPSC           0x00010000 /* local power status change */
 308#define RH_HS_OCIC           0x00020000 /* over current indicator change */
 309#define RH_HS_CRWE           0x80000000 /* clear remote wakeup enable */
 310
 311/* roothub.b masks */
 312#define RH_B_DR         0x0000ffff      /* device removable flags */
 313#define RH_B_PPCM       0xffff0000      /* port power control mask */
 314
 315/* roothub.a masks */
 316#define RH_A_NDP        (0xff << 0)     /* number of downstream ports */
 317#define RH_A_PSM        (1 << 8)        /* power switching mode */
 318#define RH_A_NPS        (1 << 9)        /* no power switching */
 319#define RH_A_DT         (1 << 10)       /* device type (mbz) */
 320#define RH_A_OCPM       (1 << 11)       /* over current protection mode */
 321#define RH_A_NOCP       (1 << 12)       /* no over current protection */
 322#define RH_A_POTPGT     (0xff << 24)    /* power on to power good time */
 323
 324/* urb */
 325#define N_URB_TD 48
 326typedef struct {
 327        ed_t *ed;
 328        __u16 length;           /* number of tds associated with this request */
 329        __u16 td_cnt;           /* number of tds already serviced */
 330        int state;
 331        unsigned long pipe;
 332        int actual_length;
 333        td_t *td[N_URB_TD];     /* list pointer to all corresponding TDs associated with this request */
 334} urb_priv_t;
 335#define URB_DEL 1
 336
 337/*
 338 * This is the full ohci controller description
 339 *
 340 * Note how the "proper" USB information is just
 341 * a subset of what the full implementation needs. (Linus)
 342 */
 343
 344typedef struct ohci {
 345        struct ohci_hcca *hcca; /* hcca */
 346        /*dma_addr_t hcca_dma; */
 347
 348        int irq;
 349        int disabled;           /* e.g. got a UE, we're hung */
 350        int sleeping;
 351        unsigned long flags;    /* for HC bugs */
 352
 353        struct ohci_regs *regs; /* OHCI controller's memory */
 354
 355        ed_t *ed_rm_list[2];    /* lists of all endpoints to be removed */
 356        ed_t *ed_bulktail;      /* last endpoint of bulk list */
 357        ed_t *ed_controltail;   /* last endpoint of control list */
 358        int intrstatus;
 359        __u32 hc_control;       /* copy of the hc control reg */
 360        struct usb_device *dev[32];
 361        struct virt_root_hub rh;
 362
 363        const char *slot_name;
 364} ohci_t;
 365
 366#define NUM_EDS 8               /* num of preallocated endpoint descriptors */
 367
 368struct ohci_device {
 369        ed_t ed[NUM_EDS];
 370        int ed_cnt;
 371};
 372
 373/* hcd */
 374/* endpoint */
 375static int ep_link(ohci_t * ohci, ed_t * ed);
 376static int ep_unlink(ohci_t * ohci, ed_t * ed);
 377static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
 378
 379/*-------------------------------------------------------------------------*/
 380
 381/* we need more TDs than EDs */
 382#define NUM_TD 64
 383
 384/* +1 so we can align the storage */
 385td_t gtd[NUM_TD + 1];
 386/* pointers to aligned storage */
 387td_t *ptd;
 388
 389/* TDs ... */
 390static inline struct td *td_alloc(struct usb_device *usb_dev)
 391{
 392        int i;
 393        struct td *td;
 394
 395        td = NULL;
 396        for (i = 0; i < NUM_TD; i++) {
 397                if (ptd[i].usb_dev == NULL) {
 398                        td = &ptd[i];
 399                        td->usb_dev = usb_dev;
 400                        break;
 401                }
 402        }
 403
 404        return td;
 405}
 406
 407static inline void ed_free(struct ed *ed)
 408{
 409        ed->usb_dev = NULL;
 410}
 411