LXR uboot/board/theadorable/theadorable.c

   1/*
   2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <i2c.h>
   9#include <pci.h>
  10#include <asm/gpio.h>
  11#include <asm/io.h>
  12#include <asm/arch/cpu.h>
  13#include <asm/arch/soc.h>
  14#include <linux/crc8.h>
  15#include <linux/mbus.h>
  16#ifdef CONFIG_NET
  17#include <netdev.h>
  18#endif
  19#include "theadorable.h"
  20
  21#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
  22#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
  23
  24DECLARE_GLOBAL_DATA_PTR;
  25
  26#define MV_USB_PHY_BASE                 (MVEBU_AXP_USB_BASE + 0x800)
  27#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
  28        (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
  29
  30#define THEADORABLE_GPP_OUT_ENA_LOW     0x00336780
  31#define THEADORABLE_GPP_OUT_ENA_MID     0x00003cf0
  32#define THEADORABLE_GPP_OUT_ENA_HIGH    (~(0x0))
  33
  34#define THEADORABLE_GPP_OUT_VAL_LOW     0x2c0c983f
  35#define THEADORABLE_GPP_OUT_VAL_MID     0x0007000c
  36#define THEADORABLE_GPP_OUT_VAL_HIGH    0x00000000
  37
  38#define GPIO_USB0_PWR_ON                18
  39#define GPIO_USB1_PWR_ON                19
  40
  41#define PEX_SWITCH_NOT_FOUNT_LIMIT      3
  42
  43#define STM_I2C_BUS     1
  44#define STM_I2C_ADDR    0x27
  45#define REBOOT_DELAY    1000            /* reboot-delay in ms */
  46
  47/* DDR3 static configuration */
  48static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
  49        {0x00001400, 0x7301ca28},       /* DDR SDRAM Configuration Register */
  50        {0x00001404, 0x30000800},       /* Dunit Control Low Register */
  51        {0x00001408, 0x44149887},       /* DDR SDRAM Timing (Low) Register */
  52        {0x0000140C, 0x38d93fc7},       /* DDR SDRAM Timing (High) Register */
  53        {0x00001410, 0x1b100001},       /* DDR SDRAM Address Control Register */
  54        {0x00001424, 0x0000f3ff},       /* Dunit Control High Register */
  55        {0x00001428, 0x000f8830},       /* ODT Timing (Low) Register */
  56        {0x0000142C, 0x014c50f4},       /* DDR3 Timing Register */
  57        {0x0000147C, 0x0000c671},       /* ODT Timing (High) Register */
  58
  59        {0x00001494, 0x00010000},       /* DDR SDRAM ODT Control (Low) Reg */
  60        {0x0000149C, 0x00000001},       /* DDR Dunit ODT Control Register */
  61        {0x000014A0, 0x00000001},       /* DRAM FIFO Control Register */
  62        {0x000014A8, 0x00000101},       /* AXI Control Register */
  63
  64        /*
  65         * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
  66         * training sequence
  67         */
  68        {0x000200e8, 0x3fff0e01},
  69        {0x00020184, 0x3fffffe0},       /* Close fast path Window to - 2G */
  70
  71        {0x0001504, 0x7fffffe1},        /* CS0 Size */
  72        {0x000150C, 0x00000000},        /* CS1 Size */
  73        {0x0001514, 0x00000000},        /* CS2 Size */
  74        {0x000151C, 0x00000000},        /* CS3 Size */
  75
  76        {0x00020220, 0x00000007},       /* Reserved */
  77
  78        {0x00001538, 0x00000009},       /* Read Data Sample Delays Register */
  79        {0x0000153C, 0x00000009},       /* Read Data Ready Delay Register */
  80
  81        {0x000015D0, 0x00000650},       /* MR0 */
  82        {0x000015D4, 0x00000044},       /* MR1 */
  83        {0x000015D8, 0x00000010},       /* MR2 */
  84        {0x000015DC, 0x00000000},       /* MR3 */
  85        {0x000015E0, 0x00000001},
  86        {0x000015E4, 0x00203c18},       /* ZQDS Configuration Register */
  87        {0x000015EC, 0xf800a225},       /* DDR PHY */
  88
  89        /* Recommended Settings from Marvell for 4 x 16 bit devices: */
  90        {0x000014C0, 0x192424c9},       /* DRAM addr and Ctrl Driving Strenght*/
  91        {0x000014C4, 0x0aaa24c9},       /* DRAM Data and DQS Driving Strenght */
  92
  93        {0x0, 0x0}
  94};
  95
  96static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
  97        {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable,  NULL},
  98};
  99
 100extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
 101
 102/*
 103 * Lane0 - PCIE0.0 X1 (to WIFI Module)
 104 * Lane5 - SATA0
 105 * Lane6 - SATA1
 106 * Lane7 - SGMII0 (to Ethernet Phy)
 107 * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
 108 * all other lanes are disabled
 109 */
 110MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
 111        { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
 112          { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
 113            PEX_BUS_DISABLED },
 114          0x0060, serdes_change_m_phy
 115        },
 116};
 117
 118MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
 119{
 120        /* Only one mode supported for this board */
 121        return &board_ddr_modes[0];
 122}
 123
 124MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
 125{
 126        return &theadorable_serdes_cfg[0];
 127}
 128
 129int board_early_init_f(void)
 130{
 131        /* Configure MPP */
 132        writel(0x00000000, MVEBU_MPP_BASE + 0x00);
 133        writel(0x03300000, MVEBU_MPP_BASE + 0x04);
 134        writel(0x00000033, MVEBU_MPP_BASE + 0x08);
 135        writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
 136        writel(0x11110000, MVEBU_MPP_BASE + 0x10);
 137        writel(0x00221100, MVEBU_MPP_BASE + 0x14);
 138        writel(0x00000000, MVEBU_MPP_BASE + 0x18);
 139        writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
 140        writel(0x00000000, MVEBU_MPP_BASE + 0x20);
 141
 142        /* Configure GPIO */
 143        writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
 144        writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
 145        writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
 146        writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
 147        writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
 148        writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
 149
 150        return 0;
 151}
 152
 153int board_init(void)
 154{
 155        int ret;
 156
 157        /* adress of boot parameters */
 158        gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 159
 160        /*
 161         * Map SPI devices via MBUS so that they can be accessed via
 162         * the SPI direct access mode
 163         */
 164        mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
 165                          CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
 166        mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
 167                          CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
 168
 169        /*
 170         * Set RX Channel Control 0 Register:
 171         * Tests have shown, that setting the LPF_COEF from 0 (1/8)
 172         * to 3 (1/1) results in a more stable USB connection.
 173         */
 174        setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
 175        setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
 176        setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
 177
 178        /* Toggle USB power */
 179        ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
 180        if (ret < 0)
 181                return ret;
 182        gpio_direction_output(GPIO_USB0_PWR_ON, 0);
 183        ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
 184        if (ret < 0)
 185                return ret;
 186        gpio_direction_output(GPIO_USB1_PWR_ON, 0);
 187        mdelay(1);
 188        gpio_set_value(GPIO_USB0_PWR_ON, 1);
 189        gpio_set_value(GPIO_USB1_PWR_ON, 1);
 190
 191        return 0;
 192}
 193
 194int checkboard(void)
 195{
 196        board_fpga_add();
 197
 198        return 0;
 199}
 200
 201#ifdef CONFIG_NET
 202int board_eth_init(bd_t *bis)
 203{
 204        cpu_eth_init(bis); /* Built in controller(s) come first */
 205        return pci_eth_init(bis);
 206}
 207#endif
 208
 209int board_video_init(void)
 210{
 211        struct mvebu_lcd_info lcd_info;
 212
 213        /* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */
 214        lcd_info.fb_base        = gd->ram_size;
 215        lcd_info.x_res          = 240;
 216        lcd_info.x_fp           = 1;
 217        lcd_info.x_bp           = 45;
 218        lcd_info.y_res          = 320;
 219        lcd_info.y_fp           = 1;
 220        lcd_info.y_bp           = 3;
 221
 222        return mvebu_lcd_register_init(&lcd_info);
 223}
 224
 225#ifdef CONFIG_BOARD_LATE_INIT
 226int board_late_init(void)
 227{
 228        pci_dev_t bdf;
 229        ulong bootcount;
 230
 231        /*
 232         * Check if the PEX switch is detected (somtimes its not available
 233         * on the PCIe bus). In this case, try to recover by issuing a
 234         * soft-reset or even a power-cycle, depending on the bootcounter
 235         * value.
 236         */
 237        bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
 238        if (bdf == -1) {
 239                u8 i2c_buf[8];
 240                int ret;
 241
 242                /* PEX switch not found! */
 243                bootcount = bootcount_load();
 244                printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
 245                       bootcount);
 246                if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
 247                        printf("Issuing power-switch via uC!\n");
 248
 249                        printf("Issuing power-switch via uC!\n");
 250                        i2c_set_bus_num(STM_I2C_BUS);
 251                        i2c_buf[0] = STM_I2C_ADDR << 1;
 252                        i2c_buf[1] = 0xc5;      /* cmd */
 253                        i2c_buf[2] = 0x01;      /* enable */
 254                        /* Delay before reboot */
 255                        i2c_buf[3] = REBOOT_DELAY & 0x00ff;
 256                        i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
 257                        /* Delay before shutdown */
 258                        i2c_buf[5] = 0x00;
 259                        i2c_buf[6] = 0x00;
 260                        i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
 261
 262                        ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
 263                        if (ret) {
 264                                printf("I2C write error (ret=%d)\n", ret);
 265                                printf("Issuing soft-reset...\n");
 266                                /* default handling: SOFT reset */
 267                                do_reset(NULL, 0, 0, NULL);
 268                        }
 269
 270                        /* Wait for power-cycle to occur... */
 271                        printf("Waiting for power-cycle via uC...\n");
 272                        while (1)
 273                                ;
 274                } else {
 275                        printf("Issuing soft-reset...\n");
 276                        /* default handling: SOFT reset */
 277                        do_reset(NULL, 0, 0, NULL);
 278                }
 279        }
 280
 281        return 0;
 282}
 283#endif
 284