1
2
3
4
5
6
7#include <asm/arch/clock.h>
8#include <asm/arch/crm_regs.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/mx7-pins.h>
11#include <asm/arch/sys_proto.h>
12#include <asm/gpio.h>
13#include <asm/imx-common/boot_mode.h>
14#include <asm/imx-common/iomux-v3.h>
15#include <asm/imx-common/mxc_i2c.h>
16#include <asm/io.h>
17#include <common.h>
18#include <dm.h>
19#include <dm/platform_data/serial_mxc.h>
20#include <fsl_esdhc.h>
21#include <i2c.h>
22#include <linux/sizes.h>
23#include <mmc.h>
24#include <miiphy.h>
25#include <netdev.h>
26#include <usb/ehci-ci.h>
27
28DECLARE_GLOBAL_DATA_PTR;
29
30#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
31 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
32
33#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
34 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
35
36#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
37#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
38
39#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
40
41#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
42 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
43
44#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
45 PAD_CTL_DSE_3P3V_49OHM)
46
47#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
48
49#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
50
51#ifdef CONFIG_SYS_I2C_MXC
52#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
53
54static struct i2c_pads_info i2c_pad_info1 = {
55 .scl = {
56 .i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC,
57 .gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC,
58 .gp = IMX_GPIO_NR(1, 4),
59 },
60 .sda = {
61 .i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC,
62 .gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC,
63 .gp = IMX_GPIO_NR(1, 5),
64 },
65};
66
67static struct i2c_pads_info i2c_pad_info4 = {
68 .scl = {
69 .i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | PC,
70 .gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | PC,
71 .gp = IMX_GPIO_NR(7, 8),
72 },
73 .sda = {
74 .i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | PC,
75 .gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | PC,
76 .gp = IMX_GPIO_NR(7, 9),
77 },
78};
79#endif
80
81int dram_init(void)
82{
83 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
84
85 return 0;
86}
87
88static iomux_v3_cfg_t const uart1_pads[] = {
89 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
90 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
91 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
92 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
93};
94
95static iomux_v3_cfg_t const usdhc1_pads[] = {
96 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102
103 MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
104};
105
106#ifdef CONFIG_NAND_MXS
107static iomux_v3_cfg_t const gpmi_pads[] = {
108 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
109 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
110 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
111 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
112 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
113 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
114 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
115 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
116 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
117 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
118 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
119 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
120 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
121 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
122 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
123};
124
125static void setup_gpmi_nand(void)
126{
127 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
128
129
130 set_clk_nand();
131}
132#endif
133
134static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
135 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146
147 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148};
149
150#ifdef CONFIG_VIDEO_MXS
151static iomux_v3_cfg_t const lcd_pads[] = {
152 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
153 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
154 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
155 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
156 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
157 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
158 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
159 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
160 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
161 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
162 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
163 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
164 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
165 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
166 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
167 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
168 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
169 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
170 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
171 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
172 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
173 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
174};
175
176static iomux_v3_cfg_t const backlight_pads[] = {
177
178 MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
179
180 MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
181 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
182};
183
184#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
185#define GPIO_PWM_A IMX_GPIO_NR(1, 8)
186
187static int setup_lcd(void)
188{
189 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
190
191 imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
192
193
194 gpio_request(GPIO_BL_ON, "BL_ON");
195 gpio_direction_output(GPIO_BL_ON, 1);
196
197
198 gpio_request(GPIO_PWM_A, "PWM<A>");
199 gpio_direction_output(GPIO_PWM_A, 0);
200
201 return 0;
202}
203#endif
204
205#ifdef CONFIG_FEC_MXC
206static iomux_v3_cfg_t const fec1_pads[] = {
207#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
208 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
209#else
210 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
211#endif
212 MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
213 MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
214 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
215 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
216 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
217 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
218 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
219 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
220 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
221};
222
223static void setup_iomux_fec(void)
224{
225 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
226}
227#endif
228
229static void setup_iomux_uart(void)
230{
231 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
232}
233
234#ifdef CONFIG_FSL_ESDHC
235
236#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0)
237
238static struct fsl_esdhc_cfg usdhc_cfg[] = {
239 {USDHC1_BASE_ADDR, 0, 4},
240};
241
242int board_mmc_getcd(struct mmc *mmc)
243{
244 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
245 int ret = 0;
246
247 switch (cfg->esdhc_base) {
248 case USDHC1_BASE_ADDR:
249 ret = !gpio_get_value(USDHC1_CD_GPIO);
250 break;
251 }
252
253 return ret;
254}
255
256int board_mmc_init(bd_t *bis)
257{
258 int i, ret;
259
260 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
261 switch (i) {
262 case 0:
263 imx_iomux_v3_setup_multiple_pads(
264 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
265 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
266 gpio_direction_input(USDHC1_CD_GPIO);
267 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
268 break;
269 default:
270 printf("Warning: you configured more USDHC controllers"
271 "(%d) than supported by the board\n", i + 1);
272 return -EINVAL;
273 }
274
275 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
276 if (ret)
277 return ret;
278 }
279
280 return 0;
281}
282#endif
283
284#ifdef CONFIG_FEC_MXC
285int board_eth_init(bd_t *bis)
286{
287 int ret;
288
289 setup_iomux_fec();
290
291 ret = fecmxc_initialize_multi(bis, 0,
292 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
293 if (ret)
294 printf("FEC1 MXC: %s:failed\n", __func__);
295
296 return ret;
297}
298
299static int setup_fec(void)
300{
301 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
302 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
303
304#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
305
306
307
308
309 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
310 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
311 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
312#else
313
314 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
315 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
316 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
317#endif
318
319 return set_clk_enet(ENET_50MHz);
320}
321
322int board_phy_config(struct phy_device *phydev)
323{
324 if (phydev->drv->config)
325 phydev->drv->config(phydev);
326 return 0;
327}
328#endif
329
330int board_early_init_f(void)
331{
332 setup_iomux_uart();
333
334#ifdef CONFIG_SYS_I2C_MXC
335 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
336 setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
337#endif
338
339 return 0;
340}
341
342int board_init(void)
343{
344
345 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
346
347#ifdef CONFIG_FEC_MXC
348 setup_fec();
349#endif
350
351#ifdef CONFIG_NAND_MXS
352 setup_gpmi_nand();
353#endif
354
355#ifdef CONFIG_VIDEO_MXS
356 setup_lcd();
357#endif
358
359 return 0;
360}
361
362#ifdef CONFIG_CMD_BMODE
363static const struct boot_mode board_boot_modes[] = {
364
365 {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
366 {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
367 {NULL, 0},
368};
369#endif
370
371int board_late_init(void)
372{
373#ifdef CONFIG_CMD_BMODE
374 add_board_boot_modes(board_boot_modes);
375#endif
376
377 return 0;
378}
379
380int checkboard(void)
381{
382 printf("Model: Toradex Colibri iMX7%c\n",
383 is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
384
385 return 0;
386}
387
388#ifdef CONFIG_USB_EHCI_MX7
389static iomux_v3_cfg_t const usb_otg2_pads[] = {
390 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
391};
392
393int board_ehci_hcd_init(int port)
394{
395 switch (port) {
396 case 0:
397 break;
398 case 1:
399 if (is_cpu_type(MXC_CPU_MX7S))
400 return -ENODEV;
401
402 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
403 ARRAY_SIZE(usb_otg2_pads));
404 break;
405 default:
406 return -EINVAL;
407 }
408 return 0;
409}
410#endif
411
412static struct mxc_serial_platdata mxc_serial_plat = {
413 .reg = (struct mxc_uart *)UART1_IPS_BASE_ADDR,
414 .use_dte = true,
415};
416
417U_BOOT_DEVICE(mxc_serial) = {
418 .name = "serial_mxc",
419 .platdata = &mxc_serial_plat,
420};
421
