1/* 2 * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved. 3 * Author: Tor Krill <tor@excito.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef SATA_SIL3114_H 9#define SATA_SIL3114_H 10 11struct sata_ioports { 12 unsigned long cmd_addr; 13 unsigned long data_addr; 14 unsigned long error_addr; 15 unsigned long feature_addr; 16 unsigned long nsect_addr; 17 unsigned long lbal_addr; 18 unsigned long lbam_addr; 19 unsigned long lbah_addr; 20 unsigned long device_addr; 21 unsigned long status_addr; 22 unsigned long command_addr; 23 unsigned long altstatus_addr; 24 unsigned long ctl_addr; 25 unsigned long bmdma_addr; 26 unsigned long scr_addr; 27}; 28 29struct sata_port { 30 unsigned char port_no; /* primary=0, secondary=1 */ 31 struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */ 32 unsigned char ctl_reg; 33 unsigned char last_ctl; 34 unsigned char port_state; /* 1-port is available and */ 35 /* 0-port is not available */ 36 unsigned char dev_mask; 37}; 38 39/* Missing ata defines */ 40#define ATA_CMD_STANDBY 0xE2 41#define ATA_CMD_STANDBYNOW1 0xE0 42#define ATA_CMD_IDLE 0xE3 43#define ATA_CMD_IDLEIMMEDIATE 0xE1 44 45/* Defines for SIL3114 chip */ 46 47/* PCI defines */ 48#define SIL_VEND_ID 0x1095 49#define SIL3114_DEVICE_ID 0x3114 50 51/* some vendor specific registers */ 52#define VND_SYSCONFSTAT 0x88 /* System Configuration Status and Command */ 53#define VND_SYSCONFSTAT_CHN_0_INTBLOCK (1<<22) 54#define VND_SYSCONFSTAT_CHN_1_INTBLOCK (1<<23) 55#define VND_SYSCONFSTAT_CHN_2_INTBLOCK (1<<24) 56#define VND_SYSCONFSTAT_CHN_3_INTBLOCK (1<<25) 57 58/* internal registers mapped by BAR5 */ 59/* SATA Control*/ 60#define VND_SCONTROL_CH0 0x100 61#define VND_SCONTROL_CH1 0x180 62#define VND_SCONTROL_CH2 0x300 63#define VND_SCONTROL_CH3 0x380 64 65#define SATA_SC_IPM_T2P (1<<16) 66#define SATA_SC_IPM_T2S (2<<16) 67#define SATA_SC_SPD_1_5 (1<<4) 68#define SATA_SC_SPD_3_0 (2<<4) 69#define SATA_SC_DET_RST (1) /* ATA Reset sequence */ 70#define SATA_SC_DET_PDIS (4) /* PHY Disable */ 71 72/* SATA Status */ 73#define VND_SSTATUS_CH0 0x104 74#define VND_SSTATUS_CH1 0x184 75#define VND_SSTATUS_CH2 0x304 76#define VND_SSTATUS_CH3 0x384 77 78#define SATA_SS_IPM_ACTIVE (1<<8) 79#define SATA_SS_IPM_PARTIAL (2<<8) 80#define SATA_SS_IPM_SLUMBER (6<<8) 81#define SATA_SS_SPD_1_5 (1<<4) 82#define SATA_SS_SPD_3_0 (2<<4) 83#define SATA_DET_P_NOPHY (1) /* Device presence but no PHY connection established */ 84#define SATA_DET_PRES (3) /* Device presence and active PHY */ 85#define SATA_DET_OFFLINE (4) /* Device offline or in loopback mode */ 86 87/* Task file registers in BAR5 mapping */ 88#define VND_TF0_CH0 0x80 89#define VND_TF0_CH1 0xc0 90#define VND_TF0_CH2 0x280 91#define VND_TF0_CH3 0x2c0 92#define VND_TF1_CH0 0x88 93#define VND_TF1_CH1 0xc8 94#define VND_TF1_CH2 0x288 95#define VND_TF1_CH3 0x2c8 96#define VND_TF2_CH0 0x88 97#define VND_TF2_CH1 0xc8 98#define VND_TF2_CH2 0x288 99#define VND_TF2_CH3 0x2c8 100 101#define VND_BMDMA_CH0 0x00 102#define VND_BMDMA_CH1 0x08 103#define VND_BMDMA_CH2 0x200 104#define VND_BMDMA_CH3 0x208 105#define VND_BMDMA2_CH0 0x10 106#define VND_BMDMA2_CH1 0x18 107#define VND_BMDMA2_CH2 0x210 108#define VND_BMDMA2_CH3 0x218 109 110/* FIFO control */ 111#define VND_FIFOCFG_CH0 0x40 112#define VND_FIFOCFG_CH1 0x44 113#define VND_FIFOCFG_CH2 0x240 114#define VND_FIFOCFG_CH3 0x244 115 116/* Task File configuration and status */ 117#define VND_TF_CNST_CH0 0xa0 118#define VND_TF_CNST_CH1 0xe0 119#define VND_TF_CNST_CH2 0x2a0 120#define VND_TF_CNST_CH3 0x2e0 121 122#define VND_TF_CNST_BFCMD (1<<1) 123#define VND_TF_CNST_CHNRST (1<<2) 124#define VND_TF_CNST_VDMA (1<<10) 125#define VND_TF_CNST_INTST (1<<11) 126#define VND_TF_CNST_WDTO (1<<12) 127#define VND_TF_CNST_WDEN (1<<13) 128#define VND_TF_CNST_WDIEN (1<<14) 129 130/* for testing */ 131#define VND_SSDR 0x04c /* System Software Data Register */ 132#define VND_FMACS 0x050 /* Flash Memory Address control and status */ 133 134#endif 135