LXR uboot/drivers/ddr/marvell/a38x/xor.h

   1/*
   2 * Copyright (C) Marvell International Ltd. and its affiliates
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0
   5 */
   6
   7#ifndef _XOR_H
   8#define _XOR_H
   9
  10#define SRAM_BASE               0x40000000
  11
  12#include "ddr3_hws_hw_training_def.h"
  13
  14#define MV_XOR_MAX_UNIT         2       /* XOR unit == XOR engine */
  15#define MV_XOR_MAX_CHAN         4       /* total channels for all units */
  16#define MV_XOR_MAX_CHAN_PER_UNIT 2      /* channels for units */
  17
  18#define MV_IS_POWER_OF_2(num)   (((num) != 0) && (((num) & ((num) - 1)) == 0))
  19
  20/*
  21 * This structure describes address space window. Window base can be
  22 * 64 bit, window size up to 4GB
  23 */
  24struct addr_win {
  25        u32 base_low;           /* 32bit base low       */
  26        u32 base_high;          /* 32bit base high      */
  27        u32 size;               /* 32bit size           */
  28};
  29
  30/* This structure describes SoC units address decode window     */
  31struct unit_win_info {
  32        struct addr_win addr_win;       /* An address window */
  33        int enable;             /* Address decode window is enabled/disabled  */
  34        u8 attrib;              /* chip select attributes */
  35        u8 target_id;           /* Target Id of this MV_TARGET */
  36};
  37
  38/*
  39 * This enumerator describes the type of functionality the XOR channel
  40 * can have while using the same data structures.
  41 */
  42enum xor_type {
  43        MV_XOR,                 /* XOR channel functions as XOR accelerator   */
  44        MV_DMA,                 /* XOR channel functions as IDMA channel      */
  45        MV_CRC32                /* XOR channel functions as CRC 32 calculator */
  46};
  47
  48enum mv_state {
  49        MV_IDLE,
  50        MV_ACTIVE,
  51        MV_PAUSED,
  52        MV_UNDEFINED_STATE
  53};
  54
  55/*
  56 * This enumerator describes the set of commands that can be applied on
  57 * an engine (e.g. IDMA, XOR). Appling a comman depends on the current
  58 * status (see MV_STATE enumerator)
  59 *
  60 * Start can be applied only when status is IDLE
  61 * Stop can be applied only when status is IDLE, ACTIVE or PAUSED
  62 * Pause can be applied only when status is ACTIVE
  63 * Restart can be applied only when status is PAUSED
  64 */
  65enum mv_command {
  66        MV_START,               /* Start     */
  67        MV_STOP,                /* Stop     */
  68        MV_PAUSE,               /* Pause    */
  69        MV_RESTART              /* Restart  */
  70};
  71
  72enum xor_override_target {
  73        SRC_ADDR0,              /* Source Address #0 Control */
  74        SRC_ADDR1,              /* Source Address #1 Control */
  75        SRC_ADDR2,              /* Source Address #2 Control */
  76        SRC_ADDR3,              /* Source Address #3 Control */
  77        SRC_ADDR4,              /* Source Address #4 Control */
  78        SRC_ADDR5,              /* Source Address #5 Control */
  79        SRC_ADDR6,              /* Source Address #6 Control */
  80        SRC_ADDR7,              /* Source Address #7 Control */
  81        XOR_DST_ADDR,           /* Destination Address Control */
  82        XOR_NEXT_DESC           /* Next Descriptor Address Control */
  83};
  84
  85enum mv_state mv_xor_state_get(u32 chan);
  86void mv_xor_hal_init(u32 xor_chan_num);
  87int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
  88int mv_xor_command_set(u32 chan, enum mv_command command);
  89int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num,
  90                        int enable);
  91
  92#endif
  93