1
2
3
4
5
6
7
8#include <common.h>
9#include <clk.h>
10#include <fdtdec.h>
11#include <mmc.h>
12#include <dm/device.h>
13#include <linux/compat.h>
14#include <linux/io.h>
15#include <linux/sizes.h>
16#include <asm/unaligned.h>
17#include <asm/dma-mapping.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21#define UNIPHIER_SD_CMD 0x000
22#define UNIPHIER_SD_CMD_NOSTOP BIT(14)
23#define UNIPHIER_SD_CMD_MULTI BIT(13)
24#define UNIPHIER_SD_CMD_RD BIT(12)
25#define UNIPHIER_SD_CMD_DATA BIT(11)
26#define UNIPHIER_SD_CMD_APP BIT(6)
27#define UNIPHIER_SD_CMD_NORMAL (0 << 8)
28#define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)
29#define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)
30#define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)
31#define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)
32#define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)
33#define UNIPHIER_SD_ARG 0x008
34#define UNIPHIER_SD_STOP 0x010
35#define UNIPHIER_SD_STOP_SEC BIT(8)
36#define UNIPHIER_SD_STOP_STP BIT(0)
37#define UNIPHIER_SD_SECCNT 0x014
38#define UNIPHIER_SD_RSP10 0x018
39#define UNIPHIER_SD_RSP32 0x020
40#define UNIPHIER_SD_RSP54 0x028
41#define UNIPHIER_SD_RSP76 0x030
42#define UNIPHIER_SD_INFO1 0x038
43#define UNIPHIER_SD_INFO1_CD BIT(5)
44#define UNIPHIER_SD_INFO1_INSERT BIT(4)
45#define UNIPHIER_SD_INFO1_REMOVE BIT(3)
46#define UNIPHIER_SD_INFO1_CMP BIT(2)
47#define UNIPHIER_SD_INFO1_RSP BIT(0)
48#define UNIPHIER_SD_INFO2 0x03c
49#define UNIPHIER_SD_INFO2_ERR_ILA BIT(15)
50#define UNIPHIER_SD_INFO2_CBSY BIT(14)
51#define UNIPHIER_SD_INFO2_BWE BIT(9)
52#define UNIPHIER_SD_INFO2_BRE BIT(8)
53#define UNIPHIER_SD_INFO2_DAT0 BIT(7)
54#define UNIPHIER_SD_INFO2_ERR_RTO BIT(6)
55#define UNIPHIER_SD_INFO2_ERR_ILR BIT(5)
56#define UNIPHIER_SD_INFO2_ERR_ILW BIT(4)
57#define UNIPHIER_SD_INFO2_ERR_TO BIT(3)
58#define UNIPHIER_SD_INFO2_ERR_END BIT(2)
59#define UNIPHIER_SD_INFO2_ERR_CRC BIT(1)
60#define UNIPHIER_SD_INFO2_ERR_IDX BIT(0)
61#define UNIPHIER_SD_INFO1_MASK 0x040
62#define UNIPHIER_SD_INFO2_MASK 0x044
63#define UNIPHIER_SD_CLKCTL 0x048
64#define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff
65#define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16)
66#define UNIPHIER_SD_CLKCTL_DIV512 BIT(7)
67#define UNIPHIER_SD_CLKCTL_DIV256 BIT(6)
68#define UNIPHIER_SD_CLKCTL_DIV128 BIT(5)
69#define UNIPHIER_SD_CLKCTL_DIV64 BIT(4)
70#define UNIPHIER_SD_CLKCTL_DIV32 BIT(3)
71#define UNIPHIER_SD_CLKCTL_DIV16 BIT(2)
72#define UNIPHIER_SD_CLKCTL_DIV8 BIT(1)
73#define UNIPHIER_SD_CLKCTL_DIV4 BIT(0)
74#define UNIPHIER_SD_CLKCTL_DIV2 0
75#define UNIPHIER_SD_CLKCTL_DIV1 BIT(10)
76#define UNIPHIER_SD_CLKCTL_OFFEN BIT(9)
77#define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8)
78#define UNIPHIER_SD_SIZE 0x04c
79#define UNIPHIER_SD_OPTION 0x050
80#define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13)
81#define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13)
82#define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13)
83#define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13)
84#define UNIPHIER_SD_BUF 0x060
85#define UNIPHIER_SD_EXTMODE 0x1b0
86#define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1)
87#define UNIPHIER_SD_SOFT_RST 0x1c0
88#define UNIPHIER_SD_SOFT_RST_RSTX BIT(0)
89#define UNIPHIER_SD_VERSION 0x1c4
90#define UNIPHIER_SD_VERSION_IP 0xff
91#define UNIPHIER_SD_HOST_MODE 0x1c8
92#define UNIPHIER_SD_IF_MODE 0x1cc
93#define UNIPHIER_SD_IF_MODE_DDR BIT(0)
94#define UNIPHIER_SD_VOLT 0x1e4
95#define UNIPHIER_SD_VOLT_MASK (3 << 0)
96#define UNIPHIER_SD_VOLT_OFF (0 << 0)
97#define UNIPHIER_SD_VOLT_330 (1 << 0)
98#define UNIPHIER_SD_VOLT_180 (2 << 0)
99#define UNIPHIER_SD_DMA_MODE 0x410
100#define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16)
101#define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0)
102#define UNIPHIER_SD_DMA_CTL 0x414
103#define UNIPHIER_SD_DMA_CTL_START BIT(0)
104#define UNIPHIER_SD_DMA_RST 0x418
105#define UNIPHIER_SD_DMA_RST_RD BIT(9)
106#define UNIPHIER_SD_DMA_RST_WR BIT(8)
107#define UNIPHIER_SD_DMA_INFO1 0x420
108#define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20)
109#define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17)
110#define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16)
111#define UNIPHIER_SD_DMA_INFO1_MASK 0x424
112#define UNIPHIER_SD_DMA_INFO2 0x428
113#define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17)
114#define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16)
115#define UNIPHIER_SD_DMA_INFO2_MASK 0x42c
116#define UNIPHIER_SD_DMA_ADDR_L 0x440
117#define UNIPHIER_SD_DMA_ADDR_H 0x444
118
119
120#define UNIPHIER_SD_DMA_MINALIGN 0x10
121
122struct uniphier_sd_priv {
123 struct mmc_config cfg;
124 struct mmc *mmc;
125 void __iomem *regbase;
126 unsigned long mclk;
127 unsigned int version;
128 u32 caps;
129#define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0)
130#define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1)
131#define UNIPHIER_SD_CAP_DIV1024 BIT(2)
132};
133
134static dma_addr_t __dma_map_single(void *ptr, size_t size,
135 enum dma_data_direction dir)
136{
137 unsigned long addr = (unsigned long)ptr;
138
139 if (dir == DMA_FROM_DEVICE)
140 invalidate_dcache_range(addr, addr + size);
141 else
142 flush_dcache_range(addr, addr + size);
143
144 return addr;
145}
146
147static void __dma_unmap_single(dma_addr_t addr, size_t size,
148 enum dma_data_direction dir)
149{
150 if (dir != DMA_TO_DEVICE)
151 invalidate_dcache_range(addr, addr + size);
152}
153
154static int uniphier_sd_check_error(struct udevice *dev)
155{
156 struct uniphier_sd_priv *priv = dev_get_priv(dev);
157 u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2);
158
159 if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) {
160
161
162
163
164
165 return -ETIMEDOUT;
166 }
167
168 if (info2 & UNIPHIER_SD_INFO2_ERR_TO) {
169 dev_err(dev, "timeout error\n");
170 return -ETIMEDOUT;
171 }
172
173 if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC |
174 UNIPHIER_SD_INFO2_ERR_IDX)) {
175 dev_err(dev, "communication out of sync\n");
176 return -EILSEQ;
177 }
178
179 if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR |
180 UNIPHIER_SD_INFO2_ERR_ILW)) {
181 dev_err(dev, "illegal access\n");
182 return -EIO;
183 }
184
185 return 0;
186}
187
188static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
189 u32 flag)
190{
191 struct uniphier_sd_priv *priv = dev_get_priv(dev);
192 long wait = 1000000;
193 int ret;
194
195 while (!(readl(priv->regbase + reg) & flag)) {
196 if (wait-- < 0) {
197 dev_err(dev, "timeout\n");
198 return -ETIMEDOUT;
199 }
200
201 ret = uniphier_sd_check_error(dev);
202 if (ret)
203 return ret;
204
205 udelay(1);
206 }
207
208 return 0;
209}
210
211static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
212 uint blocksize)
213{
214 struct uniphier_sd_priv *priv = dev_get_priv(dev);
215 int i, ret;
216
217
218 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
219 UNIPHIER_SD_INFO2_BRE);
220 if (ret)
221 return ret;
222
223
224
225
226
227 writel(0, priv->regbase + UNIPHIER_SD_INFO2);
228
229 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
230 for (i = 0; i < blocksize / 4; i++)
231 *(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF);
232 } else {
233 for (i = 0; i < blocksize / 4; i++)
234 put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF),
235 (*pbuf)++);
236 }
237
238 return 0;
239}
240
241static int uniphier_sd_pio_write_one_block(struct udevice *dev,
242 const u32 **pbuf, uint blocksize)
243{
244 struct uniphier_sd_priv *priv = dev_get_priv(dev);
245 int i, ret;
246
247
248 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
249 UNIPHIER_SD_INFO2_BWE);
250 if (ret)
251 return ret;
252
253 writel(0, priv->regbase + UNIPHIER_SD_INFO2);
254
255 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
256 for (i = 0; i < blocksize / 4; i++)
257 writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF);
258 } else {
259 for (i = 0; i < blocksize / 4; i++)
260 writel(get_unaligned((*pbuf)++),
261 priv->regbase + UNIPHIER_SD_BUF);
262 }
263
264 return 0;
265}
266
267static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
268{
269 u32 *dest = (u32 *)data->dest;
270 const u32 *src = (const u32 *)data->src;
271 int i, ret;
272
273 for (i = 0; i < data->blocks; i++) {
274 if (data->flags & MMC_DATA_READ)
275 ret = uniphier_sd_pio_read_one_block(dev, &dest,
276 data->blocksize);
277 else
278 ret = uniphier_sd_pio_write_one_block(dev, &src,
279 data->blocksize);
280 if (ret)
281 return ret;
282 }
283
284 return 0;
285}
286
287static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv,
288 dma_addr_t dma_addr)
289{
290 u32 tmp;
291
292 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1);
293 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO2);
294
295
296 tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
297 tmp |= UNIPHIER_SD_EXTMODE_DMA_EN;
298 writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
299
300 writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_L);
301
302
303 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
304
305 writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_H);
306
307 writel(UNIPHIER_SD_DMA_CTL_START, priv->regbase + UNIPHIER_SD_DMA_CTL);
308}
309
310static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
311 unsigned int blocks)
312{
313 struct uniphier_sd_priv *priv = dev_get_priv(dev);
314 long wait = 1000000 + 10 * blocks;
315
316 while (!(readl(priv->regbase + UNIPHIER_SD_DMA_INFO1) & flag)) {
317 if (wait-- < 0) {
318 dev_err(dev, "timeout during DMA\n");
319 return -ETIMEDOUT;
320 }
321
322 udelay(10);
323 }
324
325 if (readl(priv->regbase + UNIPHIER_SD_DMA_INFO2)) {
326 dev_err(dev, "error during DMA\n");
327 return -EIO;
328 }
329
330 return 0;
331}
332
333static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
334{
335 struct uniphier_sd_priv *priv = dev_get_priv(dev);
336 size_t len = data->blocks * data->blocksize;
337 void *buf;
338 enum dma_data_direction dir;
339 dma_addr_t dma_addr;
340 u32 poll_flag, tmp;
341 int ret;
342
343 tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
344
345 if (data->flags & MMC_DATA_READ) {
346 buf = data->dest;
347 dir = DMA_FROM_DEVICE;
348 poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2;
349 tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD;
350 } else {
351 buf = (void *)data->src;
352 dir = DMA_TO_DEVICE;
353 poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR;
354 tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD;
355 }
356
357 writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
358
359 dma_addr = __dma_map_single(buf, len, dir);
360
361 uniphier_sd_dma_start(priv, dma_addr);
362
363 ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
364
365 __dma_unmap_single(dma_addr, len, dir);
366
367 return ret;
368}
369
370
371static bool uniphier_sd_addr_is_dmaable(unsigned long addr)
372{
373 if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN))
374 return false;
375
376#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
377 defined(CONFIG_SPL_BUILD)
378
379
380
381
382 if (addr < CONFIG_SPL_STACK)
383 return false;
384#endif
385
386 return true;
387}
388
389static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
390 struct mmc_data *data)
391{
392 struct uniphier_sd_priv *priv = dev_get_priv(dev);
393 int ret;
394 u32 tmp;
395
396 if (readl(priv->regbase + UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
397 dev_err(dev, "command busy\n");
398 return -EBUSY;
399 }
400
401
402 writel(0, priv->regbase + UNIPHIER_SD_INFO1);
403 writel(0, priv->regbase + UNIPHIER_SD_INFO2);
404
405
406 tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
407 tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN;
408 writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
409
410 writel(cmd->cmdarg, priv->regbase + UNIPHIER_SD_ARG);
411
412 tmp = cmd->cmdidx;
413
414 if (data) {
415 writel(data->blocksize, priv->regbase + UNIPHIER_SD_SIZE);
416 writel(data->blocks, priv->regbase + UNIPHIER_SD_SECCNT);
417
418
419 tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA;
420
421 if (data->blocks > 1)
422 tmp |= UNIPHIER_SD_CMD_MULTI;
423
424 if (data->flags & MMC_DATA_READ)
425 tmp |= UNIPHIER_SD_CMD_RD;
426 }
427
428
429
430
431
432
433
434 switch (cmd->resp_type) {
435 case MMC_RSP_NONE:
436 tmp |= UNIPHIER_SD_CMD_RSP_NONE;
437 break;
438 case MMC_RSP_R1:
439 tmp |= UNIPHIER_SD_CMD_RSP_R1;
440 break;
441 case MMC_RSP_R1b:
442 tmp |= UNIPHIER_SD_CMD_RSP_R1B;
443 break;
444 case MMC_RSP_R2:
445 tmp |= UNIPHIER_SD_CMD_RSP_R2;
446 break;
447 case MMC_RSP_R3:
448 tmp |= UNIPHIER_SD_CMD_RSP_R3;
449 break;
450 default:
451 dev_err(dev, "unknown response type\n");
452 return -EINVAL;
453 }
454
455 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
456 cmd->cmdidx, tmp, cmd->cmdarg);
457 writel(tmp, priv->regbase + UNIPHIER_SD_CMD);
458
459 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
460 UNIPHIER_SD_INFO1_RSP);
461 if (ret)
462 return ret;
463
464 if (cmd->resp_type & MMC_RSP_136) {
465 u32 rsp_127_104 = readl(priv->regbase + UNIPHIER_SD_RSP76);
466 u32 rsp_103_72 = readl(priv->regbase + UNIPHIER_SD_RSP54);
467 u32 rsp_71_40 = readl(priv->regbase + UNIPHIER_SD_RSP32);
468 u32 rsp_39_8 = readl(priv->regbase + UNIPHIER_SD_RSP10);
469
470 cmd->response[0] = (rsp_127_104 & 0xffffff) << 8 |
471 (rsp_103_72 & 0xff);
472 cmd->response[1] = (rsp_103_72 & 0xffffff) << 8 |
473 (rsp_71_40 & 0xff);
474 cmd->response[2] = (rsp_71_40 & 0xffffff) << 8 |
475 (rsp_39_8 & 0xff);
476 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
477 } else {
478
479 cmd->response[0] = readl(priv->regbase + UNIPHIER_SD_RSP10);
480 }
481
482 if (data) {
483
484 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL &&
485 uniphier_sd_addr_is_dmaable((long)data->src))
486 ret = uniphier_sd_dma_xfer(dev, data);
487 else
488 ret = uniphier_sd_pio_xfer(dev, data);
489
490 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
491 UNIPHIER_SD_INFO1_CMP);
492 if (ret)
493 return ret;
494 }
495
496 return ret;
497}
498
499static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv,
500 struct mmc *mmc)
501{
502 u32 val, tmp;
503
504 switch (mmc->bus_width) {
505 case 1:
506 val = UNIPHIER_SD_OPTION_WIDTH_1;
507 break;
508 case 4:
509 val = UNIPHIER_SD_OPTION_WIDTH_4;
510 break;
511 case 8:
512 val = UNIPHIER_SD_OPTION_WIDTH_8;
513 break;
514 default:
515 return -EINVAL;
516 }
517
518 tmp = readl(priv->regbase + UNIPHIER_SD_OPTION);
519 tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK;
520 tmp |= val;
521 writel(tmp, priv->regbase + UNIPHIER_SD_OPTION);
522
523 return 0;
524}
525
526static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
527 struct mmc *mmc)
528{
529 u32 tmp;
530
531 tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE);
532 if (mmc->ddr_mode)
533 tmp |= UNIPHIER_SD_IF_MODE_DDR;
534 else
535 tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
536 writel(tmp, priv->regbase + UNIPHIER_SD_IF_MODE);
537}
538
539static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
540 struct mmc *mmc)
541{
542 unsigned int divisor;
543 u32 val, tmp;
544
545 if (!mmc->clock)
546 return;
547
548 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
549
550 if (divisor <= 1)
551 val = UNIPHIER_SD_CLKCTL_DIV1;
552 else if (divisor <= 2)
553 val = UNIPHIER_SD_CLKCTL_DIV2;
554 else if (divisor <= 4)
555 val = UNIPHIER_SD_CLKCTL_DIV4;
556 else if (divisor <= 8)
557 val = UNIPHIER_SD_CLKCTL_DIV8;
558 else if (divisor <= 16)
559 val = UNIPHIER_SD_CLKCTL_DIV16;
560 else if (divisor <= 32)
561 val = UNIPHIER_SD_CLKCTL_DIV32;
562 else if (divisor <= 64)
563 val = UNIPHIER_SD_CLKCTL_DIV64;
564 else if (divisor <= 128)
565 val = UNIPHIER_SD_CLKCTL_DIV128;
566 else if (divisor <= 256)
567 val = UNIPHIER_SD_CLKCTL_DIV256;
568 else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024))
569 val = UNIPHIER_SD_CLKCTL_DIV512;
570 else
571 val = UNIPHIER_SD_CLKCTL_DIV1024;
572
573 tmp = readl(priv->regbase + UNIPHIER_SD_CLKCTL);
574 if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN &&
575 (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val)
576 return;
577
578
579 tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
580 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
581
582 tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK;
583 tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN;
584 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
585
586 tmp |= UNIPHIER_SD_CLKCTL_SCLKEN;
587 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
588
589 udelay(1000);
590}
591
592static int uniphier_sd_set_ios(struct udevice *dev)
593{
594 struct uniphier_sd_priv *priv = dev_get_priv(dev);
595 struct mmc *mmc = mmc_get_mmc_dev(dev);
596 int ret;
597
598 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
599 mmc->clock, mmc->ddr_mode, mmc->bus_width);
600
601 ret = uniphier_sd_set_bus_width(priv, mmc);
602 if (ret)
603 return ret;
604 uniphier_sd_set_ddr_mode(priv, mmc);
605 uniphier_sd_set_clk_rate(priv, mmc);
606
607 return 0;
608}
609
610static int uniphier_sd_get_cd(struct udevice *dev)
611{
612 struct uniphier_sd_priv *priv = dev_get_priv(dev);
613
614 if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE)
615 return 1;
616
617 return !!(readl(priv->regbase + UNIPHIER_SD_INFO1) &
618 UNIPHIER_SD_INFO1_CD);
619}
620
621static const struct dm_mmc_ops uniphier_sd_ops = {
622 .send_cmd = uniphier_sd_send_cmd,
623 .set_ios = uniphier_sd_set_ios,
624 .get_cd = uniphier_sd_get_cd,
625};
626
627static void uniphier_sd_host_init(struct uniphier_sd_priv *priv)
628{
629 u32 tmp;
630
631
632 tmp = readl(priv->regbase + UNIPHIER_SD_SOFT_RST);
633 tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX;
634 writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
635 tmp |= UNIPHIER_SD_SOFT_RST_RSTX;
636 writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
637
638
639
640 writel(UNIPHIER_SD_STOP_SEC, priv->regbase + UNIPHIER_SD_STOP);
641
642
643
644
645
646
647 writel(priv->version >= 0x10 ? 0x00000101 : 0x00000000,
648 priv->regbase + UNIPHIER_SD_HOST_MODE);
649
650 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) {
651 tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
652 tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
653 writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
654 }
655}
656
657static int uniphier_sd_probe(struct udevice *dev)
658{
659 struct uniphier_sd_priv *priv = dev_get_priv(dev);
660 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
661 fdt_addr_t base;
662 struct clk clk;
663 int ret;
664
665 base = dev_get_addr(dev);
666 if (base == FDT_ADDR_T_NONE)
667 return -EINVAL;
668
669 priv->regbase = devm_ioremap(dev, base, SZ_2K);
670 if (!priv->regbase)
671 return -ENOMEM;
672
673 ret = clk_get_by_index(dev, 0, &clk);
674 if (ret < 0) {
675 dev_err(dev, "failed to get host clock\n");
676 return ret;
677 }
678
679
680 priv->mclk = clk_set_rate(&clk, ULONG_MAX);
681 if (IS_ERR_VALUE(priv->mclk)) {
682 dev_err(dev, "failed to set rate for host clock\n");
683 clk_free(&clk);
684 return priv->mclk;
685 }
686
687 ret = clk_enable(&clk);
688 clk_free(&clk);
689 if (ret) {
690 dev_err(dev, "failed to enable host clock\n");
691 return ret;
692 }
693
694 priv->cfg.name = dev->name;
695 priv->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
696
697 switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) {
698 case 8:
699 priv->cfg.host_caps |= MMC_MODE_8BIT;
700 break;
701 case 4:
702 priv->cfg.host_caps |= MMC_MODE_4BIT;
703 break;
704 case 1:
705 break;
706 default:
707 dev_err(dev, "Invalid \"bus-width\" value\n");
708 return -EINVAL;
709 }
710
711 if (fdt_get_property(gd->fdt_blob, dev->of_offset, "non-removable",
712 NULL))
713 priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
714
715 priv->version = readl(priv->regbase + UNIPHIER_SD_VERSION) &
716 UNIPHIER_SD_VERSION_IP;
717 dev_dbg(dev, "version %x\n", priv->version);
718 if (priv->version >= 0x10) {
719 priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
720 priv->caps |= UNIPHIER_SD_CAP_DIV1024;
721 }
722
723 uniphier_sd_host_init(priv);
724
725 priv->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
726 priv->cfg.f_min = priv->mclk /
727 (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512);
728 priv->cfg.f_max = priv->mclk;
729 priv->cfg.b_max = U32_MAX;
730
731 priv->mmc = mmc_create(&priv->cfg, priv);
732 if (!priv->mmc)
733 return -EIO;
734
735 upriv->mmc = priv->mmc;
736 priv->mmc->dev = dev;
737
738 return 0;
739}
740
741static int uniphier_sd_remove(struct udevice *dev)
742{
743 struct uniphier_sd_priv *priv = dev_get_priv(dev);
744
745 mmc_destroy(priv->mmc);
746
747 return 0;
748}
749
750static const struct udevice_id uniphier_sd_match[] = {
751 { .compatible = "socionext,uniphier-sdhc" },
752 { }
753};
754
755U_BOOT_DRIVER(uniphier_mmc) = {
756 .name = "uniphier-mmc",
757 .id = UCLASS_MMC,
758 .of_match = uniphier_sd_match,
759 .probe = uniphier_sd_probe,
760 .remove = uniphier_sd_remove,
761 .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv),
762 .ops = &uniphier_sd_ops,
763};
764