1/* 2 * Error Corrected Code Controller (ECC) - System peripherals regsters. 3 * Based on AT91SAM9260 datasheet revision B. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef ATMEL_NAND_ECC_H 9#define ATMEL_NAND_ECC_H 10 11#define ATMEL_ECC_CR 0x00 /* Control register */ 12#define ATMEL_ECC_RST (1 << 0) /* Reset parity */ 13 14#define ATMEL_ECC_MR 0x04 /* Mode register */ 15#define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */ 16#define ATMEL_ECC_PAGESIZE_528 (0) 17#define ATMEL_ECC_PAGESIZE_1056 (1) 18#define ATMEL_ECC_PAGESIZE_2112 (2) 19#define ATMEL_ECC_PAGESIZE_4224 (3) 20 21#define ATMEL_ECC_SR 0x08 /* Status register */ 22#define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */ 23#define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ 24#define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */ 25 26#define ATMEL_ECC_PR 0x0c /* Parity register */ 27#define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */ 28#define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ 29 30#define ATMEL_ECC_NPR 0x10 /* NParity register */ 31#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */ 32 33/* Register access macros for PMECC */ 34#define pmecc_readl(addr, reg) \ 35 readl(&addr->reg) 36 37#define pmecc_readb(addr, reg) \ 38 readb(&addr->reg) 39 40#define pmecc_writel(addr, reg, value) \ 41 writel((value), &addr->reg) 42 43/* PMECC Register Definitions */ 44#define PMECC_MAX_SECTOR_NUM 8 45struct pmecc_regs { 46 u32 cfg; /* 0x00 PMECC Configuration Register */ 47 u32 sarea; /* 0x04 PMECC Spare Area Size Register */ 48 u32 saddr; /* 0x08 PMECC Start Address Register */ 49 u32 eaddr; /* 0x0C PMECC End Address Register */ 50 u32 clk; /* 0x10 PMECC Clock Control Register */ 51 u32 ctrl; /* 0x14 PMECC Control Register */ 52 u32 sr; /* 0x18 PMECC Status Register */ 53 u32 ier; /* 0x1C PMECC Interrupt Enable Register */ 54 u32 idr; /* 0x20 PMECC Interrupt Disable Register */ 55 u32 imr; /* 0x24 PMECC Interrupt Mask Register */ 56 u32 isr; /* 0x28 PMECC Interrupt Status Register */ 57 u32 reserved0[5]; /* 0x2C-0x3C Reserved */ 58 59 /* 0x40 + sector_num * (0x40), Redundancy Registers */ 60 struct { 61#ifdef CONFIG_SAMA5D2 62 u8 ecc[56]; /* PMECC Generated Redundancy Byte Per Sector */ 63 u32 reserved1[2]; 64#else 65 u8 ecc[44]; /* PMECC Generated Redundancy Byte Per Sector */ 66 u32 reserved1[5]; 67#endif 68 } ecc_port[PMECC_MAX_SECTOR_NUM]; 69 70 /* 0x240 + sector_num * (0x40) Remainder Registers */ 71 struct { 72#ifdef CONFIG_SAMA5D2 73 u32 rem[16]; 74#else 75 u32 rem[12]; 76 u32 reserved2[4]; 77#endif 78 } rem_port[PMECC_MAX_SECTOR_NUM]; 79 u32 reserved3[16]; /* 0x440-0x47C Reserved */ 80}; 81 82/* For PMECC Configuration Register */ 83#define PMECC_CFG_BCH_ERR2 (0 << 0) 84#define PMECC_CFG_BCH_ERR4 (1 << 0) 85#define PMECC_CFG_BCH_ERR8 (2 << 0) 86#define PMECC_CFG_BCH_ERR12 (3 << 0) 87#define PMECC_CFG_BCH_ERR24 (4 << 0) 88#define PMECC_CFG_BCH_ERR32 (5 << 0) 89 90#define PMECC_CFG_SECTOR512 (0 << 4) 91#define PMECC_CFG_SECTOR1024 (1 << 4) 92 93#define PMECC_CFG_PAGE_1SECTOR (0 << 8) 94#define PMECC_CFG_PAGE_2SECTORS (1 << 8) 95#define PMECC_CFG_PAGE_4SECTORS (2 << 8) 96#define PMECC_CFG_PAGE_8SECTORS (3 << 8) 97 98#define PMECC_CFG_READ_OP (0 << 12) 99#define PMECC_CFG_WRITE_OP (1 << 12) 100 101#define PMECC_CFG_SPARE_ENABLE (1 << 16) 102#define PMECC_CFG_SPARE_DISABLE (0 << 16) 103 104#define PMECC_CFG_AUTO_ENABLE (1 << 20) 105#define PMECC_CFG_AUTO_DISABLE (0 << 20) 106 107/* For PMECC Clock Control Register */ 108#define PMECC_CLK_133MHZ (2 << 0) 109 110/* For PMECC Control Register */ 111#define PMECC_CTRL_RST (1 << 0) 112#define PMECC_CTRL_DATA (1 << 1) 113#define PMECC_CTRL_USER (1 << 2) 114#define PMECC_CTRL_ENABLE (1 << 4) 115#define PMECC_CTRL_DISABLE (1 << 5) 116 117/* For PMECC Status Register */ 118#define PMECC_SR_BUSY (1 << 0) 119#define PMECC_SR_ENABLE (1 << 4) 120 121/* PMERRLOC Register Definitions */ 122struct pmecc_errloc_regs { 123 u32 elcfg; /* 0x00 Error Location Configuration Register */ 124 u32 elprim; /* 0x04 Error Location Primitive Register */ 125 u32 elen; /* 0x08 Error Location Enable Register */ 126 u32 eldis; /* 0x0C Error Location Disable Register */ 127 u32 elsr; /* 0x10 Error Location Status Register */ 128 u32 elier; /* 0x14 Error Location Interrupt Enable Register */ 129 u32 elidr; /* 0x08 Error Location Interrupt Disable Register */ 130 u32 elimr; /* 0x0C Error Location Interrupt Mask Register */ 131 u32 elisr; /* 0x20 Error Location Interrupt Status Register */ 132 u32 reserved0; /* 0x24 Reserved */ 133#ifdef CONFIG_SAMA5D2 134 u32 sigma[33]; /* 0x28-0xA8 Error Location Sigma Registers */ 135 u32 el[32]; /* 0xAC-0x128 Error Location Registers */ 136 137 /* 138 * 0x12C-0x1FC: 139 * Reserved for SAMA5D2. 140 */ 141 u32 reserved1[53]; 142#else 143 u32 sigma[25]; /* 0x28-0x88 Error Location Sigma Registers */ 144 u32 el[24]; /* 0x8C-0xE8 Error Location Registers */ 145 u32 reserved1[5]; /* 0xEC-0xFC Reserved */ 146#endif 147 148 /* 149 * SAMA5 chip HSMC registers start here. But for 9X5 chip it is just 150 * reserved. 151 * 152 * Offset 0x00-0xF8: 153 */ 154 u32 reserved2[63]; 155 156 /* 157 * Offset 0xFC: 158 * PMECC version for AT91SAM9X5, AT91SAM9N12. 159 * HSMC version for SAMA5D3, SAMA5D4. Can refer as PMECC version. 160 */ 161 u32 version; 162}; 163 164/* For Error Location Configuration Register */ 165#define PMERRLOC_ELCFG_SECTOR_512 (0 << 0) 166#define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0) 167#define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16) 168 169/* For Error Location Disable Register */ 170#define PMERRLOC_DISABLE (1 << 0) 171 172/* For Error Location Interrupt Status Register */ 173#ifdef CONFIG_SAMA5D2 174#define PMERRLOC_ERR_NUM_MASK (0x3f << 8) 175#else 176#define PMERRLOC_ERR_NUM_MASK (0x1f << 8) 177#endif 178 179#define PMERRLOC_CALC_DONE (1 << 0) 180 181/* PMECC IP version */ 182#define PMECC_VERSION_SAMA5D2 0x210 183#define PMECC_VERSION_SAMA5D4 0x113 184#define PMECC_VERSION_SAMA5D3 0x112 185#define PMECC_VERSION_AT91SAM9N12 0x102 186#define PMECC_VERSION_AT91SAM9X5 0x101 187 188/* Galois field dimension */ 189#define PMECC_GF_DIMENSION_13 13 190#define PMECC_GF_DIMENSION_14 14 191 192/* Primitive Polynomial used by PMECC */ 193#define PMECC_GF_13_PRIMITIVE_POLY 0x201b 194#define PMECC_GF_14_PRIMITIVE_POLY 0x4443 195 196#define PMECC_INDEX_TABLE_SIZE_512 0x2000 197#define PMECC_INDEX_TABLE_SIZE_1024 0x4000 198 199#define PMECC_MAX_TIMEOUT_US (100 * 1000) 200 201/* Reserved bytes in oob area */ 202#define PMECC_OOB_RESERVED_BYTES 2 203 204#endif 205