1/* 2 * Configuation settings for the Freescale MCF52277 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * board/config.h - configuration options, board specific 12 */ 13 14#ifndef _M52277EVB_H 15#define _M52277EVB_H 16 17/* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21#define CONFIG_M52277EVB /* M52277EVB board */ 22 23#define CONFIG_MCFUART 24#define CONFIG_SYS_UART_PORT (0) 25#define CONFIG_BAUDRATE 115200 26 27#undef CONFIG_WATCHDOG 28 29#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31/* 32 * BOOTP options 33 */ 34#define CONFIG_BOOTP_BOOTFILESIZE 35#define CONFIG_BOOTP_BOOTPATH 36#define CONFIG_BOOTP_GATEWAY 37#define CONFIG_BOOTP_HOSTNAME 38 39/* Command line configuration */ 40#define CONFIG_CMD_DATE 41#define CONFIG_CMD_JFFS2 42#define CONFIG_CMD_REGINFO 43#undef CONFIG_CMD_BMP 44 45#define CONFIG_HOSTNAME M52277EVB 46#define CONFIG_SYS_UBOOT_END 0x3FFFF 47#define CONFIG_SYS_LOAD_ADDR2 0x40010007 48#ifdef CONFIG_SYS_STMICRO_BOOT 49/* ST Micro serial flash */ 50#define CONFIG_EXTRA_ENV_SETTINGS \ 51 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 52 "loadaddr=0x40010000\0" \ 53 "uboot=u-boot.bin\0" \ 54 "load=loadb ${loadaddr} ${baudrate};" \ 55 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 56 "upd=run load; run prog\0" \ 57 "prog=sf probe 0:2 10000 1;" \ 58 "sf erase 0 30000;" \ 59 "sf write ${loadaddr} 0 30000;" \ 60 "save\0" \ 61 "" 62#endif 63#ifdef CONFIG_SYS_SPANSION_BOOT 64#define CONFIG_EXTRA_ENV_SETTINGS \ 65 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 66 "loadaddr=0x40010000\0" \ 67 "uboot=u-boot.bin\0" \ 68 "load=loadb ${loadaddr} ${baudrate}\0" \ 69 "upd=run load; run prog\0" \ 70 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 71 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 72 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 73 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 74 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 75 " ${filesize}; save\0" \ 76 "updsbf=run loadsbf; run progsbf\0" \ 77 "loadsbf=loadb ${loadaddr} ${baudrate};" \ 78 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 79 "progsbf=sf probe 0:2 10000 1;" \ 80 "sf erase 0 30000;" \ 81 "sf write ${loadaddr} 0 30000;" \ 82 "" 83#endif 84 85/* LCD */ 86#ifdef CONFIG_CMD_BMP 87#define CONFIG_LCD 88#define CONFIG_SPLASH_SCREEN 89#define CONFIG_LCD_LOGO 90#define CONFIG_SHARP_LQ035Q7DH06 91#endif 92 93/* USB */ 94#ifdef CONFIG_CMD_USB 95#define CONFIG_USB_EHCI 96#define CONFIG_DOS_PARTITION 97#define CONFIG_MAC_PARTITION 98#define CONFIG_ISO_PARTITION 99#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 100#define CONFIG_SYS_USB_EHCI_CPU_INIT 101#endif 102 103/* Realtime clock */ 104#define CONFIG_MCFRTC 105#undef RTC_DEBUG 106#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 107 108/* Timer */ 109#define CONFIG_MCFTMR 110#undef CONFIG_MCFPIT 111 112/* I2c */ 113#define CONFIG_SYS_I2C 114#define CONFIG_SYS_I2C_FSL 115#define CONFIG_SYS_FSL_I2C_SPEED 80000 116#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 117#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 118#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 119 120/* DSPI and Serial Flash */ 121#define CONFIG_CF_SPI 122#define CONFIG_CF_DSPI 123#define CONFIG_HARD_SPI 124#define CONFIG_SYS_SBFHDR_SIZE 0x7 125#ifdef CONFIG_CMD_SPI 126# define CONFIG_SYS_DSPI_CS2 127 128# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 129 DSPI_CTAR_PCSSCK_1CLK | \ 130 DSPI_CTAR_PASC(0) | \ 131 DSPI_CTAR_PDT(0) | \ 132 DSPI_CTAR_CSSCK(0) | \ 133 DSPI_CTAR_ASC(0) | \ 134 DSPI_CTAR_DT(1)) 135#endif 136 137/* Input, PCI, Flexbus, and VCO */ 138#define CONFIG_EXTRA_CLOCK 139 140#define CONFIG_SYS_INPUT_CLKSRC 16000000 141 142#define CONFIG_PRAM 2048 /* 2048 KB */ 143 144#define CONFIG_SYS_LONGHELP /* undef to save memory */ 145 146#if defined(CONFIG_CMD_KGDB) 147#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 148#else 149#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 150#endif 151#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 152#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 153#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 154 155#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 156 157#define CONFIG_SYS_MBAR 0xFC000000 158 159/* 160 * Low Level Configuration Settings 161 * (address mappings, register initial values, etc.) 162 * You should know what you are doing if you make changes here. 163 */ 164 165/* 166 * Definitions for initial stack pointer and data area (in DPRAM) 167 */ 168#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 169#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 170#define CONFIG_SYS_INIT_RAM_CTRL 0x221 171#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 172#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 173#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 174 175/* 176 * Start addresses for the final memory configuration 177 * (Set up by the startup code) 178 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 179 */ 180#define CONFIG_SYS_SDRAM_BASE 0x40000000 181#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 182#define CONFIG_SYS_SDRAM_CFG1 0x43711630 183#define CONFIG_SYS_SDRAM_CFG2 0x56670000 184#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 185#define CONFIG_SYS_SDRAM_EMOD 0x81810000 186#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 187#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 188 189#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 190#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 191 192#ifdef CONFIG_CF_SBF 193# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 194#else 195# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 196#endif 197#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 198#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 199#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 200 201/* Initial Memory map for Linux */ 202#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 203#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 204 205/* 206 * Configuration for environment 207 * Environment is not embedded in u-boot. First time runing may have env 208 * crc error warning if there is no correct environment on the flash. 209 */ 210#ifdef CONFIG_CF_SBF 211# define CONFIG_ENV_IS_IN_SPI_FLASH 212# define CONFIG_ENV_SPI_CS 2 213#else 214# define CONFIG_ENV_IS_IN_FLASH 1 215#endif 216#define CONFIG_ENV_OVERWRITE 1 217 218/*----------------------------------------------------------------------- 219 * FLASH organization 220 */ 221#ifdef CONFIG_SYS_STMICRO_BOOT 222# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 223# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 224# define CONFIG_ENV_OFFSET 0x30000 225# define CONFIG_ENV_SIZE 0x1000 226# define CONFIG_ENV_SECT_SIZE 0x10000 227#endif 228#ifdef CONFIG_SYS_SPANSION_BOOT 229# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 230# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 231# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 232# define CONFIG_ENV_SIZE 0x1000 233# define CONFIG_ENV_SECT_SIZE 0x8000 234#endif 235 236#define CONFIG_SYS_FLASH_CFI 237#ifdef CONFIG_SYS_FLASH_CFI 238# define CONFIG_FLASH_CFI_DRIVER 1 239# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 240# define CONFIG_FLASH_SPANSION_S29WS_N 1 241# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 242# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 243# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 244# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 245# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 246# define CONFIG_SYS_FLASH_CHECKSUM 247# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 248#endif 249 250#define LDS_BOARD_TEXT \ 251 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ 252 arch/m68k/lib/built-in.o (.text*) 253 254/* 255 * This is setting for JFFS2 support in u-boot. 256 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 257 */ 258#ifdef CONFIG_CMD_JFFS2 259# define CONFIG_JFFS2_DEV "nor0" 260# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) 261# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) 262#endif 263 264/*----------------------------------------------------------------------- 265 * Cache Configuration 266 */ 267#define CONFIG_SYS_CACHELINE_SIZE 16 268 269#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 270 CONFIG_SYS_INIT_RAM_SIZE - 8) 271#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 272 CONFIG_SYS_INIT_RAM_SIZE - 4) 273#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 274#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 275 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 276 CF_ACR_EN | CF_ACR_SM_ALL) 277#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 278 CF_CACR_DISD | CF_CACR_INVI | \ 279 CF_CACR_CEIB | CF_CACR_DCM | \ 280 CF_CACR_EUSP) 281 282/*----------------------------------------------------------------------- 283 * Memory bank definitions 284 */ 285/* 286 * CS0 - NOR Flash 287 * CS1 - Available 288 * CS2 - Available 289 * CS3 - Available 290 * CS4 - Available 291 * CS5 - Available 292 */ 293 294#ifdef CONFIG_CF_SBF 295#define CONFIG_SYS_CS0_BASE 0x04000000 296#define CONFIG_SYS_CS0_MASK 0x00FF0001 297#define CONFIG_SYS_CS0_CTRL 0x00001FA0 298#else 299#define CONFIG_SYS_CS0_BASE 0x00000000 300#define CONFIG_SYS_CS0_MASK 0x00FF0001 301#define CONFIG_SYS_CS0_CTRL 0x00001FA0 302#endif 303 304#endif /* _M52277EVB_H */ 305