1/* 2 * Configuation settings for the Freescale MCF54455 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * board/config.h - configuration options, board specific 12 */ 13 14#ifndef _M54455EVB_H 15#define _M54455EVB_H 16 17/* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21#define CONFIG_M54455EVB /* M54455EVB board */ 22 23#define CONFIG_DISPLAY_BOARDINFO 24 25#define CONFIG_MCFUART 26#define CONFIG_SYS_UART_PORT (0) 27#define CONFIG_BAUDRATE 115200 28 29#undef CONFIG_WATCHDOG 30 31#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 32 33/* 34 * BOOTP options 35 */ 36#define CONFIG_BOOTP_BOOTFILESIZE 37#define CONFIG_BOOTP_BOOTPATH 38#define CONFIG_BOOTP_GATEWAY 39#define CONFIG_BOOTP_HOSTNAME 40 41/* Command line configuration */ 42#define CONFIG_CMD_DATE 43#define CONFIG_CMD_IDE 44#define CONFIG_CMD_JFFS2 45#undef CONFIG_CMD_PCI 46#define CONFIG_CMD_REGINFO 47 48/* Network configuration */ 49#define CONFIG_MCFFEC 50#ifdef CONFIG_MCFFEC 51# define CONFIG_MII 1 52# define CONFIG_MII_INIT 1 53# define CONFIG_SYS_DISCOVER_PHY 54# define CONFIG_SYS_RX_ETH_BUFFER 8 55# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56 57# define CONFIG_SYS_FEC0_PINMUX 0 58# define CONFIG_SYS_FEC1_PINMUX 0 59# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 60# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 61# define MCFFEC_TOUT_LOOP 50000 62# define CONFIG_HAS_ETH1 63 64# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" 65# define CONFIG_ETHPRIME "FEC0" 66# define CONFIG_IPADDR 192.162.1.2 67# define CONFIG_NETMASK 255.255.255.0 68# define CONFIG_SERVERIP 192.162.1.1 69# define CONFIG_GATEWAYIP 192.162.1.1 70 71/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 72# ifndef CONFIG_SYS_DISCOVER_PHY 73# define FECDUPLEX FULL 74# define FECSPEED _100BASET 75# else 76# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 77# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 78# endif 79# endif /* CONFIG_SYS_DISCOVER_PHY */ 80#endif 81 82#define CONFIG_HOSTNAME M54455EVB 83#ifdef CONFIG_SYS_STMICRO_BOOT 84/* ST Micro serial flash */ 85#define CONFIG_SYS_LOAD_ADDR2 0x40010013 86#define CONFIG_EXTRA_ENV_SETTINGS \ 87 "netdev=eth0\0" \ 88 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 89 "loadaddr=0x40010000\0" \ 90 "sbfhdr=sbfhdr.bin\0" \ 91 "uboot=u-boot.bin\0" \ 92 "load=tftp ${loadaddr} ${sbfhdr};" \ 93 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 94 "upd=run load; run prog\0" \ 95 "prog=sf probe 0:1 1000000 3;" \ 96 "sf erase 0 30000;" \ 97 "sf write ${loadaddr} 0 0x30000;" \ 98 "save\0" \ 99 "" 100#else 101/* Atmel and Intel */ 102#ifdef CONFIG_SYS_ATMEL_BOOT 103# define CONFIG_SYS_UBOOT_END 0x0403FFFF 104#elif defined(CONFIG_SYS_INTEL_BOOT) 105# define CONFIG_SYS_UBOOT_END 0x3FFFF 106#endif 107#define CONFIG_EXTRA_ENV_SETTINGS \ 108 "netdev=eth0\0" \ 109 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 110 "loadaddr=0x40010000\0" \ 111 "uboot=u-boot.bin\0" \ 112 "load=tftp ${loadaddr} ${uboot}\0" \ 113 "upd=run load; run prog\0" \ 114 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 115 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 116 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 117 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 118 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 119 " ${filesize}; save\0" \ 120 "" 121#endif 122 123/* ATA configuration */ 124#define CONFIG_ISO_PARTITION 125#define CONFIG_DOS_PARTITION 126#define CONFIG_IDE_RESET 1 127#define CONFIG_IDE_PREINIT 1 128#define CONFIG_ATAPI 129#undef CONFIG_LBA48 130 131#define CONFIG_SYS_IDE_MAXBUS 1 132#define CONFIG_SYS_IDE_MAXDEVICE 2 133 134#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 135#define CONFIG_SYS_ATA_IDE0_OFFSET 0 136 137#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 138#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 139#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 140#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 141 142/* Realtime clock */ 143#define CONFIG_MCFRTC 144#undef RTC_DEBUG 145#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 146 147/* Timer */ 148#define CONFIG_MCFTMR 149#undef CONFIG_MCFPIT 150 151/* I2c */ 152#define CONFIG_SYS_I2C 153#define CONFIG_SYS_I2C_FSL 154#define CONFIG_SYS_FSL_I2C_SPEED 80000 155#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 156#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 157#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 158 159/* DSPI and Serial Flash */ 160#define CONFIG_CF_SPI 161#define CONFIG_CF_DSPI 162#define CONFIG_HARD_SPI 163#define CONFIG_SYS_SBFHDR_SIZE 0x13 164#ifdef CONFIG_CMD_SPI 165 166# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 167 DSPI_CTAR_PCSSCK_1CLK | \ 168 DSPI_CTAR_PASC(0) | \ 169 DSPI_CTAR_PDT(0) | \ 170 DSPI_CTAR_CSSCK(0) | \ 171 DSPI_CTAR_ASC(0) | \ 172 DSPI_CTAR_DT(1)) 173#endif 174 175/* PCI */ 176#ifdef CONFIG_CMD_PCI 177#define CONFIG_PCI 1 178#define CONFIG_PCI_PNP 1 179#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 180 181#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 182 183#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 184#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 185#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 186 187#define CONFIG_SYS_PCI_IO_BUS 0xB1000000 188#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 189#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 190 191#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 192#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 193#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 194#endif 195 196/* FPGA - Spartan 2 */ 197/* experiment 198#define CONFIG_FPGA 199#define CONFIG_FPGA_COUNT 1 200#define CONFIG_SYS_FPGA_PROG_FEEDBACK 201#define CONFIG_SYS_FPGA_CHECK_CTRLC 202*/ 203 204/* Input, PCI, Flexbus, and VCO */ 205#define CONFIG_EXTRA_CLOCK 206 207#define CONFIG_PRAM 2048 /* 2048 KB */ 208 209#define CONFIG_SYS_LONGHELP /* undef to save memory */ 210 211#if defined(CONFIG_CMD_KGDB) 212#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 213#else 214#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 215#endif 216#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 217#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 218#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 219 220#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 221 222#define CONFIG_SYS_MBAR 0xFC000000 223 224/* 225 * Low Level Configuration Settings 226 * (address mappings, register initial values, etc.) 227 * You should know what you are doing if you make changes here. 228 */ 229 230/*----------------------------------------------------------------------- 231 * Definitions for initial stack pointer and data area (in DPRAM) 232 */ 233#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 234#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 235#define CONFIG_SYS_INIT_RAM_CTRL 0x221 236#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 237#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 238#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 239 240/*----------------------------------------------------------------------- 241 * Start addresses for the final memory configuration 242 * (Set up by the startup code) 243 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 244 */ 245#define CONFIG_SYS_SDRAM_BASE 0x40000000 246#define CONFIG_SYS_SDRAM_BASE1 0x48000000 247#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 248#define CONFIG_SYS_SDRAM_CFG1 0x65311610 249#define CONFIG_SYS_SDRAM_CFG2 0x59670000 250#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 251#define CONFIG_SYS_SDRAM_EMOD 0x40010000 252#define CONFIG_SYS_SDRAM_MODE 0x00010033 253#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 254 255#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 256#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 257 258#ifdef CONFIG_CF_SBF 259# define CONFIG_SERIAL_BOOT 260# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 261#else 262# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 263#endif 264#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 265#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 266 267/* Reserve 256 kB for malloc() */ 268#define CONFIG_SYS_MALLOC_LEN (256 << 10) 269 270/* 271 * For booting Linux, the board info and command line data 272 * have to be in the first 8 MB of memory, since this is 273 * the maximum mapped by the Linux kernel during initialization ?? 274 */ 275/* Initial Memory map for Linux */ 276#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 277 278/* 279 * Configuration for environment 280 * Environment is not embedded in u-boot. First time runing may have env 281 * crc error warning if there is no correct environment on the flash. 282 */ 283#ifdef CONFIG_CF_SBF 284# define CONFIG_ENV_IS_IN_SPI_FLASH 285# define CONFIG_ENV_SPI_CS 1 286#else 287# define CONFIG_ENV_IS_IN_FLASH 1 288#endif 289#undef CONFIG_ENV_OVERWRITE 290 291/*----------------------------------------------------------------------- 292 * FLASH organization 293 */ 294#ifdef CONFIG_SYS_STMICRO_BOOT 295# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 296# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 297# define CONFIG_ENV_OFFSET 0x30000 298# define CONFIG_ENV_SIZE 0x2000 299# define CONFIG_ENV_SECT_SIZE 0x10000 300#endif 301#ifdef CONFIG_SYS_ATMEL_BOOT 302# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 303# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 304# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 305# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 306# define CONFIG_ENV_SIZE 0x2000 307# define CONFIG_ENV_SECT_SIZE 0x10000 308#endif 309#ifdef CONFIG_SYS_INTEL_BOOT 310# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 311# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 312# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 313# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 314# define CONFIG_ENV_SIZE 0x2000 315# define CONFIG_ENV_SECT_SIZE 0x20000 316#endif 317 318#define CONFIG_SYS_FLASH_CFI 319#ifdef CONFIG_SYS_FLASH_CFI 320 321# define CONFIG_FLASH_CFI_DRIVER 1 322# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 323# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 324# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 325# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 326# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 327# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 328# define CONFIG_SYS_FLASH_CHECKSUM 329# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 330# define CONFIG_FLASH_CFI_LEGACY 331 332#ifdef CONFIG_FLASH_CFI_LEGACY 333# define CONFIG_SYS_ATMEL_REGION 4 334# define CONFIG_SYS_ATMEL_TOTALSECT 11 335# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 336# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 337#endif 338#endif 339 340/* 341 * This is setting for JFFS2 support in u-boot. 342 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 343 */ 344#ifdef CONFIG_CMD_JFFS2 345#ifdef CF_STMICRO_BOOT 346# define CONFIG_JFFS2_DEV "nor1" 347# define CONFIG_JFFS2_PART_SIZE 0x01000000 348# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 349#endif 350#ifdef CONFIG_SYS_ATMEL_BOOT 351# define CONFIG_JFFS2_DEV "nor1" 352# define CONFIG_JFFS2_PART_SIZE 0x01000000 353# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 354#endif 355#ifdef CONFIG_SYS_INTEL_BOOT 356# define CONFIG_JFFS2_DEV "nor0" 357# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 358# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 359#endif 360#endif 361 362/*----------------------------------------------------------------------- 363 * Cache Configuration 364 */ 365#define CONFIG_SYS_CACHELINE_SIZE 16 366 367#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 368 CONFIG_SYS_INIT_RAM_SIZE - 8) 369#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 370 CONFIG_SYS_INIT_RAM_SIZE - 4) 371#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 372#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 373#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 374 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 375 CF_ACR_EN | CF_ACR_SM_ALL) 376#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 377 CF_CACR_ICINVA | CF_CACR_EUSP) 378#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 379 CF_CACR_DEC | CF_CACR_DDCM_P | \ 380 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 381 382/*----------------------------------------------------------------------- 383 * Memory bank definitions 384 */ 385/* 386 * CS0 - NOR Flash 1, 2, 4, or 8MB 387 * CS1 - CompactFlash and registers 388 * CS2 - CPLD 389 * CS3 - FPGA 390 * CS4 - Available 391 * CS5 - Available 392 */ 393 394#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 395 /* Atmel Flash */ 396#define CONFIG_SYS_CS0_BASE 0x04000000 397#define CONFIG_SYS_CS0_MASK 0x00070001 398#define CONFIG_SYS_CS0_CTRL 0x00001140 399/* Intel Flash */ 400#define CONFIG_SYS_CS1_BASE 0x00000000 401#define CONFIG_SYS_CS1_MASK 0x01FF0001 402#define CONFIG_SYS_CS1_CTRL 0x00000D60 403 404#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 405#else 406/* Intel Flash */ 407#define CONFIG_SYS_CS0_BASE 0x00000000 408#define CONFIG_SYS_CS0_MASK 0x01FF0001 409#define CONFIG_SYS_CS0_CTRL 0x00000D60 410 /* Atmel Flash */ 411#define CONFIG_SYS_CS1_BASE 0x04000000 412#define CONFIG_SYS_CS1_MASK 0x00070001 413#define CONFIG_SYS_CS1_CTRL 0x00001140 414 415#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 416#endif 417 418/* CPLD */ 419#define CONFIG_SYS_CS2_BASE 0x08000000 420#define CONFIG_SYS_CS2_MASK 0x00070001 421#define CONFIG_SYS_CS2_CTRL 0x003f1140 422 423/* FPGA */ 424#define CONFIG_SYS_CS3_BASE 0x09000000 425#define CONFIG_SYS_CS3_MASK 0x00070001 426#define CONFIG_SYS_CS3_CTRL 0x00000020 427 428#endif /* _M54455EVB_H */ 429