1
2
3
4
5
6
7
8
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_DISPLAY_BOARDINFO
14
15
16#define CONFIG_BOOKE 1
17#define CONFIG_E500 1
18#define CONFIG_MPC8568 1
19#define CONFIG_MPC8568MDS 1
20
21#define CONFIG_SYS_TEXT_BASE 0xfff80000
22
23#define CONFIG_SYS_SRIO
24#define CONFIG_SRIO1
25
26#define CONFIG_PCI 1
27#define CONFIG_PCI1 1
28#define CONFIG_PCIE1 1
29#define CONFIG_FSL_PCI_INIT 1
30#define CONFIG_PCI_INDIRECT_BRIDGE 1
31#define CONFIG_FSL_PCIE_RESET 1
32#define CONFIG_SYS_PCI_64BIT 1
33#define CONFIG_TSEC_ENET
34#define CONFIG_QE
35#define CONFIG_ENV_OVERWRITE
36#define CONFIG_FSL_LAW 1
37
38#ifndef __ASSEMBLY__
39extern unsigned long get_clock_freq(void);
40#endif
41#define CONFIG_SYS_CLK_FREQ 66000000
42
43
44
45
46#define CONFIG_L2_CACHE
47#define CONFIG_BTB
48
49
50
51
52#define CONFIG_ENABLE_36BIT_PHYS 1
53
54#define CONFIG_BOARD_EARLY_INIT_F 1
55
56#define CONFIG_SYS_MEMTEST_START 0x00200000
57#define CONFIG_SYS_MEMTEST_END 0x00400000
58
59#define CONFIG_SYS_CCSRBAR 0xe0000000
60#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
61
62
63#define CONFIG_SYS_FSL_DDR2
64#undef CONFIG_FSL_DDR_INTERACTIVE
65#define CONFIG_SPD_EEPROM
66#define CONFIG_DDR_SPD
67#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
68
69#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
70
71#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
72#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
73
74#define CONFIG_NUM_DDR_CONTROLLERS 1
75#define CONFIG_DIMM_SLOTS_PER_CTLR 1
76#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
77
78
79#define SPD_EEPROM_ADDRESS 0x51
80
81
82#ifndef CONFIG_SPD_EEPROM
83#error ("CONFIG_SPD_EEPROM is required")
84#endif
85
86#undef CONFIG_CLOCKS_IN_MHZ
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121#define CONFIG_SYS_BCSR_BASE 0xf8000000
122
123#define CONFIG_SYS_FLASH_BASE 0xfe000000
124
125
126#define CONFIG_SYS_BR0_PRELIM 0xfe001001
127#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
128
129
130#define CONFIG_SYS_BR1_PRELIM 0xf8000801
131#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
132
133
134#define CONFIG_SYS_MAX_FLASH_BANKS 1
135#define CONFIG_SYS_MAX_FLASH_SECT 512
136#undef CONFIG_SYS_FLASH_CHECKSUM
137#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
138#define CONFIG_SYS_FLASH_WRITE_TOUT 500
139
140#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
141
142#define CONFIG_FLASH_CFI_DRIVER
143#define CONFIG_SYS_FLASH_CFI
144#define CONFIG_SYS_FLASH_EMPTY_INFO
145
146
147
148
149#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
150#define CONFIG_SYS_LBC_SDRAM_SIZE 64
151
152
153#define CONFIG_SYS_BR2_PRELIM 0xf0001861
154#define CONFIG_SYS_OR2_PRELIM 0xfc006901
155
156#define CONFIG_SYS_LBC_LCRR 0x00030004
157#define CONFIG_SYS_LBC_LBCR 0x00000000
158#define CONFIG_SYS_LBC_LSRT 0x20000000
159#define CONFIG_SYS_LBC_MRTPR 0x00000000
160
161
162
163
164
165
166
167#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
168 | LSDMR_PRETOACT7 \
169 | LSDMR_ACTTORW7 \
170 | LSDMR_BL8 \
171 | LSDMR_WRC4 \
172 | LSDMR_CL3 \
173 | LSDMR_RFEN \
174 )
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205#define CONFIG_SYS_BCSR (0xf8000000)
206
207
208#define CONFIG_SYS_BR4_PRELIM 0xf8008801
209#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
210
211
212#define CONFIG_SYS_BR5_PRELIM 0xf8010801
213#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
214
215#define CONFIG_SYS_INIT_RAM_LOCK 1
216#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
217#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
218
219#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
220#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
221
222#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
223#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
224
225
226#define CONFIG_CONS_INDEX 1
227#define CONFIG_SYS_NS16550_SERIAL
228#define CONFIG_SYS_NS16550_REG_SIZE 1
229#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
230
231#define CONFIG_SYS_BAUDRATE_TABLE \
232 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
233
234#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
235#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
236
237
238
239
240#define CONFIG_SYS_I2C
241#define CONFIG_SYS_I2C_FSL
242#define CONFIG_SYS_FSL_I2C_SPEED 400000
243#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
244#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
245#define CONFIG_SYS_FSL_I2C2_SPEED 400000
246#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
247#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
248#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
249#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
250
251
252
253
254
255#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
256#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
257#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
258#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
259#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
260#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
261#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
262#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000
263
264#define CONFIG_SYS_PCIE1_NAME "Slot"
265#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
266#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
267#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
268#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
269#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
270#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
271#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
272#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
273
274#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
275#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
276#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
277#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
278
279#ifdef CONFIG_QE
280
281
282
283#define CONFIG_UEC_ETH
284#ifndef CONFIG_TSEC_ENET
285#define CONFIG_ETHPRIME "UEC0"
286#endif
287#define CONFIG_PHY_MODE_NEED_CHANGE
288#define CONFIG_eTSEC_MDIO_BUS
289
290#ifdef CONFIG_eTSEC_MDIO_BUS
291#define CONFIG_MIIM_ADDRESS 0xE0024520
292#endif
293
294#define CONFIG_UEC_ETH1
295
296#ifdef CONFIG_UEC_ETH1
297#define CONFIG_SYS_UEC1_UCC_NUM 0
298#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
299#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
300#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
301#define CONFIG_SYS_UEC1_PHY_ADDR 7
302#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
303#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
304#endif
305
306#define CONFIG_UEC_ETH2
307
308#ifdef CONFIG_UEC_ETH2
309#define CONFIG_SYS_UEC2_UCC_NUM 1
310#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
311#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
312#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
313#define CONFIG_SYS_UEC2_PHY_ADDR 1
314#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
315#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
316#endif
317#endif
318
319#if defined(CONFIG_PCI)
320
321#define CONFIG_PCI_PNP
322
323#undef CONFIG_EEPRO100
324#undef CONFIG_TULIP
325
326#undef CONFIG_PCI_SCAN_SHOW
327#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
328
329#endif
330
331#if defined(CONFIG_TSEC_ENET)
332
333#define CONFIG_MII 1
334#define CONFIG_TSEC1 1
335#define CONFIG_TSEC1_NAME "eTSEC0"
336#define CONFIG_TSEC2 1
337#define CONFIG_TSEC2_NAME "eTSEC1"
338
339#define TSEC1_PHY_ADDR 2
340#define TSEC2_PHY_ADDR 3
341
342#define TSEC1_PHYIDX 0
343#define TSEC2_PHYIDX 0
344
345#define TSEC1_FLAGS TSEC_GIGABIT
346#define TSEC2_FLAGS TSEC_GIGABIT
347
348
349#define CONFIG_ETHPRIME "eTSEC0"
350
351#endif
352
353
354
355
356#define CONFIG_ENV_IS_IN_FLASH 1
357#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
358#define CONFIG_ENV_SECT_SIZE 0x40000
359#define CONFIG_ENV_SIZE 0x2000
360
361#define CONFIG_LOADS_ECHO 1
362#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
363
364
365
366
367#define CONFIG_BOOTP_BOOTFILESIZE
368#define CONFIG_BOOTP_BOOTPATH
369#define CONFIG_BOOTP_GATEWAY
370#define CONFIG_BOOTP_HOSTNAME
371
372
373
374
375#define CONFIG_CMD_IRQ
376#define CONFIG_CMD_REGINFO
377
378#if defined(CONFIG_PCI)
379 #define CONFIG_CMD_PCI
380#endif
381
382#undef CONFIG_WATCHDOG
383
384
385
386
387#define CONFIG_SYS_LONGHELP
388#define CONFIG_CMDLINE_EDITING
389#define CONFIG_AUTO_COMPLETE
390#define CONFIG_SYS_LOAD_ADDR 0x2000000
391#if defined(CONFIG_CMD_KGDB)
392#define CONFIG_SYS_CBSIZE 1024
393#else
394#define CONFIG_SYS_CBSIZE 256
395#endif
396#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
397#define CONFIG_SYS_MAXARGS 16
398#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
399
400
401
402
403
404
405#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
406#define CONFIG_SYS_BOOTM_LEN (64 << 20)
407
408#if defined(CONFIG_CMD_KGDB)
409#define CONFIG_KGDB_BAUDRATE 230400
410#endif
411
412
413
414
415
416
417#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
418#define CONFIG_HAS_ETH0
419#define CONFIG_HAS_ETH1
420#define CONFIG_HAS_ETH2
421#define CONFIG_HAS_ETH3
422#endif
423
424#define CONFIG_IPADDR 192.168.1.253
425
426#define CONFIG_HOSTNAME unknown
427#define CONFIG_ROOTPATH "/nfsroot"
428#define CONFIG_BOOTFILE "your.uImage"
429
430#define CONFIG_SERVERIP 192.168.1.1
431#define CONFIG_GATEWAYIP 192.168.1.1
432#define CONFIG_NETMASK 255.255.255.0
433
434#define CONFIG_LOADADDR 200000
435
436#undef CONFIG_BOOTARGS
437
438#define CONFIG_BAUDRATE 115200
439
440#define CONFIG_EXTRA_ENV_SETTINGS \
441 "netdev=eth0\0" \
442 "consoledev=ttyS0\0" \
443 "ramdiskaddr=600000\0" \
444 "ramdiskfile=your.ramdisk.u-boot\0" \
445 "fdtaddr=400000\0" \
446 "fdtfile=your.fdt.dtb\0" \
447 "nfsargs=setenv bootargs root=/dev/nfs rw " \
448 "nfsroot=$serverip:$rootpath " \
449 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
450 "console=$consoledev,$baudrate $othbootargs\0" \
451 "ramargs=setenv bootargs root=/dev/ram rw " \
452 "console=$consoledev,$baudrate $othbootargs\0" \
453
454#define CONFIG_NFSBOOTCOMMAND \
455 "run nfsargs;" \
456 "tftp $loadaddr $bootfile;" \
457 "tftp $fdtaddr $fdtfile;" \
458 "bootm $loadaddr - $fdtaddr"
459
460#define CONFIG_RAMBOOTCOMMAND \
461 "run ramargs;" \
462 "tftp $ramdiskaddr $ramdiskfile;" \
463 "tftp $loadaddr $bootfile;" \
464 "bootm $loadaddr $ramdiskaddr"
465
466#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
467
468#endif
469