1
2
3
4
5
6
7
8
9
10
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15
16
17
18
19
20#define CONFIG_405EP 1
21#define CONFIG_PLU405 1
22
23#define CONFIG_SYS_TEXT_BASE 0xFFF80000
24#define CONFIG_DISPLAY_BOARDINFO
25
26#define CONFIG_BOARD_EARLY_INIT_F 1
27#define CONFIG_MISC_INIT_R 1
28
29#define CONFIG_SYS_CLK_FREQ 33333400
30
31#define CONFIG_BAUDRATE 9600
32
33#undef CONFIG_BOOTARGS
34#undef CONFIG_BOOTCOMMAND
35
36#define CONFIG_PREBOOT
37
38#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
39
40#undef CONFIG_HAS_ETH1
41
42#define CONFIG_PPC4xx_EMAC
43#define CONFIG_MII 1
44#define CONFIG_PHY_ADDR 0
45#define CONFIG_LXT971_NO_SLEEP 1
46#define CONFIG_RESET_PHY_R 1
47
48#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
49
50
51
52
53#define CONFIG_BOOTP_BOOTFILESIZE
54#define CONFIG_BOOTP_BOOTPATH
55#define CONFIG_BOOTP_GATEWAY
56#define CONFIG_BOOTP_HOSTNAME
57
58
59
60
61#define CONFIG_CMD_PCI
62#define CONFIG_CMD_IRQ
63#define CONFIG_CMD_IDE
64#define CONFIG_CMD_NAND
65#define CONFIG_CMD_DATE
66#define CONFIG_CMD_EEPROM
67
68#define CONFIG_MAC_PARTITION
69#define CONFIG_DOS_PARTITION
70
71#define CONFIG_SUPPORT_VFAT
72
73#undef CONFIG_WATCHDOG
74
75#define CONFIG_RTC_MC146818
76#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500
77
78#define CONFIG_SDRAM_BANK0 1
79
80
81
82
83#define CONFIG_SYS_LONGHELP
84
85#if defined(CONFIG_CMD_KGDB)
86#define CONFIG_SYS_CBSIZE 1024
87#else
88#define CONFIG_SYS_CBSIZE 256
89#endif
90#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
91#define CONFIG_SYS_MAXARGS 16
92#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
93
94#define CONFIG_SYS_DEVICE_NULLDEV 1
95
96#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
97
98#define CONFIG_AUTO_COMPLETE 1
99
100#define CONFIG_SYS_MEMTEST_START 0x0400000
101#define CONFIG_SYS_MEMTEST_END 0x0C00000
102
103#define CONFIG_CONS_INDEX 1
104#define CONFIG_SYS_NS16550_SERIAL
105#define CONFIG_SYS_NS16550_REG_SIZE 1
106#define CONFIG_SYS_NS16550_CLK get_serial_clock()
107
108#undef CONFIG_SYS_EXT_SERIAL_CLOCK
109#define CONFIG_SYS_BASE_BAUD 691200
110
111
112#define CONFIG_SYS_BAUDRATE_TABLE \
113 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
114 57600, 115200, 230400, 460800, 921600 }
115
116#define CONFIG_SYS_LOAD_ADDR 0x100000
117#define CONFIG_SYS_EXTBDINFO 1
118
119#define CONFIG_CMDLINE_EDITING 1
120
121#define CONFIG_SYS_RX_ETH_BUFFER 16
122
123
124
125
126#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
127#define CONFIG_SYS_MAX_NAND_DEVICE 1
128#define NAND_BIG_DELAY_US 25
129
130#define CONFIG_SYS_NAND_CE (0x80000000 >> 1)
131#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)
132#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)
133#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)
134
135#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1
136#define CONFIG_SYS_NAND_QUIET 1
137
138
139
140
141#define PCI_HOST_ADAPTER 0
142#define PCI_HOST_FORCE 1
143#define PCI_HOST_AUTO 2
144
145#define CONFIG_PCI
146#define CONFIG_PCI_INDIRECT_BRIDGE
147#define CONFIG_PCI_HOST PCI_HOST_FORCE
148#define CONFIG_PCI_PNP
149
150
151#define CONFIG_PCI_SCAN_SHOW
152
153#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1
154
155#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
156#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405
157#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
158#define CONFIG_SYS_PCI_PTM1LA 0x00000000
159#define CONFIG_SYS_PCI_PTM1MS 0xf8000001
160#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
161#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
162#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
163#define CONFIG_SYS_PCI_PTM2PCI 0x08000000
164
165
166
167
168#undef CONFIG_IDE_8xx_DIRECT
169#undef CONFIG_IDE_LED
170#define CONFIG_IDE_RESET 1
171
172#define CONFIG_SYS_IDE_MAXBUS 1
173
174#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
175
176#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
177#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
178
179#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
180#define CONFIG_SYS_ATA_REG_OFFSET 0x0000
181#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
182
183
184
185
186
187
188#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
189
190
191
192
193#define FLASH_BASE0_PRELIM 0xFFC00000
194
195#define CONFIG_SYS_MAX_FLASH_BANKS 1
196#define CONFIG_SYS_MAX_FLASH_SECT 256
197
198#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
199#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
200
201#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
202#define CONFIG_SYS_FLASH_ADDR0 0x5555
203#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
204
205
206
207
208#define CONFIG_SYS_FLASH_READ0 0x0000
209#define CONFIG_SYS_FLASH_READ1 0x0001
210#define CONFIG_SYS_FLASH_READ2 0x0002
211
212#define CONFIG_SYS_FLASH_EMPTY_INFO
213
214
215
216
217
218
219#define CONFIG_SYS_SDRAM_BASE 0x00000000
220#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
221#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
222#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
223#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
224
225
226
227
228#define CONFIG_ENV_IS_IN_EEPROM 1
229#define CONFIG_ENV_OFFSET 0x100
230#define CONFIG_ENV_SIZE 0x700
231
232
233
234
235#define CONFIG_SYS_I2C
236#define CONFIG_SYS_I2C_PPC4XX
237#define CONFIG_SYS_I2C_PPC4XX_CH0
238#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
239#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
240
241#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
242#define CONFIG_SYS_EEPROM_WREN 1
243
244
245#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
246
247#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
248#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
249
250
251#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
252
253
254
255
256#define CAN0_BA 0xF0000000
257#define CAN1_BA 0xF0000100
258#define DUART0_BA 0xF0000400
259#define DUART1_BA 0xF0000408
260#define RTC_BA 0xF0000500
261#define VGA_BA 0xF1000000
262#define CONFIG_SYS_NAND_BASE 0xF4000000
263
264
265
266#define CONFIG_SYS_EBC_PB0AP 0x92015480
267
268#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
269
270
271#define CONFIG_SYS_EBC_PB1AP 0x92015480
272
273#define CONFIG_SYS_EBC_PB1CR 0xF4018000
274
275
276
277#define CONFIG_SYS_EBC_PB2AP 0x010053C0
278
279#define CONFIG_SYS_EBC_PB2CR 0xF0018000
280
281
282
283#define CONFIG_SYS_EBC_PB3AP 0x010053C0
284
285#define CONFIG_SYS_EBC_PB3CR 0xF011A000
286
287
288
289
290#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100
291
292
293#define CONFIG_SYS_FPGA_CTRL 0x000
294
295
296#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
297#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
298#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
299
300#define CONFIG_SYS_FPGA_SPARTAN2 1
301#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024
302
303
304#define CONFIG_SYS_FPGA_PRG 0x04000000
305#define CONFIG_SYS_FPGA_CLK 0x02000000
306#define CONFIG_SYS_FPGA_DATA 0x01000000
307#define CONFIG_SYS_FPGA_INIT 0x00010000
308#define CONFIG_SYS_FPGA_DONE 0x00008000
309
310
311
312
313
314#define CONFIG_SYS_TEMP_STACK_OCM 1
315
316
317#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
318#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
319#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
320#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
321
322#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
323#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
324
325
326
327
328
329
330
331
332
333
334
335
336
337#define CONFIG_SYS_GPIO0_OSRL 0x00000550
338#define CONFIG_SYS_GPIO0_OSRH 0x00000110
339#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
340#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
341#define CONFIG_SYS_GPIO0_TSRL 0x00000000
342#define CONFIG_SYS_GPIO0_TSRH 0x00000000
343#define CONFIG_SYS_GPIO0_TCR 0x77FE0014
344
345#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
346#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
347
348
349
350
351
352#if 1
353#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
354#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
355#endif
356#if 0
357#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
358#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
359#endif
360#if 0
361#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
362#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
363#endif
364
365
366
367
368#define CONFIG_USB_OHCI_NEW 1
369#define CONFIG_PCI_OHCI 1
370#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
371#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
372#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
373
374
375
376
377#define CONFIG_CMD_UBI
378#define CONFIG_RBTREE
379#define CONFIG_MTD_DEVICE
380#define CONFIG_MTD_PARTITIONS
381#define CONFIG_CMD_MTDPARTS
382#define CONFIG_LZO
383
384#endif
385