LXR uboot/include/configs/PMC440.h

   1/*
   2 * (C) Copyright 2007-2008
   3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4 * Based on the sequoia configuration file.
   5 *
   6 * (C) Copyright 2006-2007
   7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8 *
   9 * (C) Copyright 2006
  10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11 * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  12 *
  13 * SPDX-License-Identifier:     GPL-2.0+
  14 */
  15
  16/************************************************************************
  17 * PMC440.h - configuration for esd PMC440 boards
  18 ***********************************************************************/
  19#ifndef __CONFIG_H
  20#define __CONFIG_H
  21
  22/*-----------------------------------------------------------------------
  23 * High Level Configuration Options
  24 *----------------------------------------------------------------------*/
  25#define CONFIG_440EPX           1       /* Specific PPC440EPx   */
  26#define CONFIG_440              1       /* ... PPC440 family    */
  27
  28#ifndef CONFIG_SYS_TEXT_BASE
  29#define CONFIG_SYS_TEXT_BASE    0xFFF90000
  30#endif
  31
  32#define CONFIG_DISPLAY_BOARDINFO
  33
  34#define CONFIG_SYS_CLK_FREQ     33333400
  35
  36#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
  37#define CONFIG_4xx_DCACHE               /* enable dcache        */
  38#endif
  39
  40#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f */
  41#define CONFIG_MISC_INIT_F      1
  42#define CONFIG_MISC_INIT_R      1       /* Call misc_init_r     */
  43#define CONFIG_BOARD_TYPES      1       /* support board types  */
  44/*-----------------------------------------------------------------------
  45 * Base addresses -- Note these are effective addresses where the
  46 * actual resources get mapped (not physical addresses)
  47 *----------------------------------------------------------------------*/
  48#define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
  49#define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 256 kB for malloc()  */
  50
  51#define CONFIG_PRAM             0       /* use pram variable to overwrite */
  52
  53#define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  54#define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  55#define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  56#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  57#define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  58#define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  59#define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  60#define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  61#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  62#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  63#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  64#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  65#define CONFIG_SYS_PCI_MEMSIZE          0x80000000      /* 2GB! */
  66
  67#define CONFIG_SYS_USB2D0_BASE          0xe0000100
  68#define CONFIG_SYS_USB_DEVICE           0xe0000000
  69#define CONFIG_SYS_USB_HOST             0xe0000400
  70#define CONFIG_SYS_FPGA_BASE0           0xef000000      /* 32 bit */
  71#define CONFIG_SYS_FPGA_BASE1           0xef100000      /* 16 bit */
  72#define CONFIG_SYS_RESET_BASE           0xef200000
  73
  74/*-----------------------------------------------------------------------
  75 * Initial RAM & stack pointer
  76 *----------------------------------------------------------------------*/
  77/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  78#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  79#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  80#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  81#define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  82
  83/*-----------------------------------------------------------------------
  84 * Serial Port
  85 *----------------------------------------------------------------------*/
  86#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  87#define CONFIG_SYS_NS16550_SERIAL
  88#define CONFIG_SYS_NS16550_REG_SIZE     1
  89#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  90#undef CONFIG_SYS_EXT_SERIAL_CLOCK
  91#define CONFIG_BAUDRATE         115200
  92
  93#define CONFIG_SYS_BAUDRATE_TABLE                                               \
  94        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  95
  96/*-----------------------------------------------------------------------
  97 * Environment
  98 *----------------------------------------------------------------------*/
  99#define CONFIG_ENV_IS_IN_EEPROM 1       /* use FLASH for environment vars */
 100
 101/*-----------------------------------------------------------------------
 102 * RTC
 103 *----------------------------------------------------------------------*/
 104#define CONFIG_RTC_RX8025
 105
 106/*-----------------------------------------------------------------------
 107 * FLASH related
 108 *----------------------------------------------------------------------*/
 109#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 110#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver        */
 111
 112#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 113
 114#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 115#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 116
 117#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 118#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 119
 120#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 121#define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 122
 123#define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on flinfo */
 124#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 125
 126#ifdef CONFIG_ENV_IS_IN_FLASH
 127#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 128#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 129#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 130
 131/* Address and size of Redundant Environment Sector     */
 132#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 133#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 134#endif
 135
 136#ifdef CONFIG_ENV_IS_IN_EEPROM
 137#define CONFIG_I2C_ENV_EEPROM_BUS       0
 138#define CONFIG_ENV_OFFSET               0       /* environment starts at the beginning of the EEPROM */
 139#define CONFIG_ENV_SIZE         0x1000  /* 4096 bytes may be used for env vars */
 140#endif
 141
 142/*-----------------------------------------------------------------------
 143 * DDR SDRAM
 144 *----------------------------------------------------------------------*/
 145#define CONFIG_DDR_DATA_EYE     /* use DDR2 optimization        */
 146#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
 147                                                  /* 440EPx errata CHIP 11 */
 148
 149/*-----------------------------------------------------------------------
 150 * I2C
 151 *----------------------------------------------------------------------*/
 152#define CONFIG_SYS_I2C
 153#define CONFIG_SYS_I2C_PPC4XX
 154#define CONFIG_SYS_I2C_PPC4XX_CH0
 155#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 156#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 157#define CONFIG_SYS_I2C_PPC4XX_CH1
 158#define CONFIG_SYS_I2C_PPC4XX_SPEED_1           400000
 159#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1           0x7F
 160
 161#define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 162#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 163#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 164#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 165#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x01
 166
 167#define CONFIG_SYS_EEPROM_WREN                  1
 168#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 169
 170/*
 171 * standard dtt sensor configuration - bottom bit will determine local or
 172 * remote sensor of the TMP401
 173 */
 174#define CONFIG_DTT_SENSORS              { 0, 1 }
 175
 176/*
 177 * The PMC440 uses a TI TMP401 temperature sensor. This part
 178 * is basically compatible to the ADM1021 that is supported
 179 * by U-Boot.
 180 *
 181 * - i2c addr 0x4c
 182 * - conversion rate 0x02 = 0.25 conversions/second
 183 * - ALERT ouput disabled
 184 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
 185 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
 186 */
 187#define CONFIG_DTT_ADM1021
 188#define CONFIG_SYS_DTT_ADM1021          { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 189
 190#define CONFIG_PREBOOT          "echo Add \\\"run fpga\\\" and "        \
 191                                "\\\"painit\\\" to preboot command"
 192
 193#undef  CONFIG_BOOTARGS
 194
 195/* Setup some board specific values for the default environment variables */
 196#define CONFIG_HOSTNAME         pmc440
 197#define CONFIG_SYS_BOOTFILE     "bootfile=/tftpboot/pmc440/uImage\0"
 198#define CONFIG_SYS_ROOTPATH     "rootpath=/opt/eldk/ppc_4xxFP\0"
 199
 200#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 201        CONFIG_SYS_BOOTFILE                                             \
 202        CONFIG_SYS_ROOTPATH                                             \
 203        "fdt_file=/tftpboot/pmc440/pmc440.dtb\0"                        \
 204        "netdev=eth0\0"                                                 \
 205        "ethrotate=no\0"                                                \
 206        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 207        "nfsroot=${serverip}:${rootpath}\0"                             \
 208        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 209        "addip=setenv bootargs ${bootargs} "                            \
 210                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 211                ":${hostname}:${netdev}:off panic=1\0"                  \
 212        "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 213        "addmisc=setenv bootargs ${bootargs} mem=${mem}\0"              \
 214        "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
 215        "nand_boot_fdt=run nandargs addip addtty addmisc;"              \
 216                "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 217        "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"                \
 218                "tftp  ${fdt_addr_r} ${fdt_file};"                      \
 219                "run nfsargs addip addtty addmisc;"                     \
 220                "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 221        "kernel_addr=ffc00000\0"                                        \
 222        "kernel_addr_r=200000\0"                                        \
 223        "fpga_addr=fff00000\0"                                          \
 224        "fdt_addr=fff80000\0"                                           \
 225        "fdt_addr_r=800000\0"                                           \
 226        "fpga=fpga loadb 0 ${fpga_addr}\0"                              \
 227        "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"                \
 228        "update=protect off fff90000 ffffffff;era fff90000 ffffffff;"   \
 229                "cp.b 200000 fff90000 70000\0"                          \
 230        ""
 231
 232
 233#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 234#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 235
 236#define CONFIG_PPC4xx_EMAC
 237#define CONFIG_IBM_EMAC4_V4     1
 238#define CONFIG_MII              1       /* MII PHY management           */
 239#define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 240
 241#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 242
 243#define CONFIG_HAS_ETH0
 244#define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 245
 246#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 247#define CONFIG_PHY1_ADDR        1
 248#define CONFIG_RESET_PHY_R      1
 249
 250/* USB */
 251#define CONFIG_USB_OHCI_NEW
 252#define CONFIG_SYS_OHCI_BE_CONTROLLER
 253
 254#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
 255#define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 256#define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 257#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 258#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 259
 260/* Comment this out to enable USB 1.1 device */
 261#define USB_2_0_DEVICE
 262
 263/* Partitions */
 264#define CONFIG_MAC_PARTITION
 265#define CONFIG_DOS_PARTITION
 266#define CONFIG_ISO_PARTITION
 267
 268#define CONFIG_CMD_BSP
 269#define CONFIG_CMD_DATE
 270#define CONFIG_CMD_DTT
 271#define CONFIG_CMD_EEPROM
 272#define CONFIG_CMD_NAND
 273#define CONFIG_CMD_PCI
 274#define CONFIG_CMD_REGINFO
 275
 276/* POST support */
 277#define CONFIG_POST             (CONFIG_SYS_POST_MEMORY |       \
 278                                 CONFIG_SYS_POST_CPU    |       \
 279                                 CONFIG_SYS_POST_UART   |       \
 280                                 CONFIG_SYS_POST_I2C    |       \
 281                                 CONFIG_SYS_POST_CACHE  |       \
 282                                 CONFIG_SYS_POST_FPU    |       \
 283                                 CONFIG_SYS_POST_ETHER  |       \
 284                                 CONFIG_SYS_POST_SPR)
 285
 286#define CONFIG_LOGBUFFER
 287#define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 288
 289#define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* Otherwise it catches logbuffer as output */
 290
 291#define CONFIG_SUPPORT_VFAT
 292
 293/*-----------------------------------------------------------------------
 294 * Miscellaneous configurable options
 295 *----------------------------------------------------------------------*/
 296#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 297#if defined(CONFIG_CMD_KGDB)
 298#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 299#else
 300#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 301#endif
 302#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 303#define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 304#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 305
 306#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on          */
 307#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM       */
 308
 309#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address      */
 310#define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 311
 312#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 313#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 314
 315/*-----------------------------------------------------------------------
 316 * PCI stuff
 317 *----------------------------------------------------------------------*/
 318/* General PCI */
 319#define CONFIG_PCI              /* include pci support          */
 320#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 321#define CONFIG_PCI_PNP          /* do (not) pci plug-and-play   */
 322#define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 323#define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup  */
 324#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 325
 326/* Board-specific PCI */
 327#define CONFIG_SYS_PCI_TARGET_INIT
 328#define CONFIG_SYS_PCI_MASTER_INIT
 329#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 330
 331#define CONFIG_PCI_BOOTDELAY 0
 332
 333/* PCI identification */
 334#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 335#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441      /* PCI Device ID: Non-Monarch */
 336#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
 337/* for weak __pci_target_init() */
 338#define CONFIG_SYS_PCI_SUBSYS_ID        CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 339#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH     PCI_CLASS_PROCESSOR_POWERPC
 340#define CONFIG_SYS_PCI_CLASSCODE_MONARCH        PCI_CLASS_BRIDGE_HOST
 341
 342/*
 343 * For booting Linux, the board info and command line data
 344 * have to be in the first 8 MB of memory, since this is
 345 * the maximum mapped by the Linux kernel during initialization.
 346 */
 347#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 348
 349/*-----------------------------------------------------------------------
 350 * FPGA stuff
 351 *----------------------------------------------------------------------*/
 352#define CONFIG_FPGA
 353#define CONFIG_FPGA_XILINX
 354#define CONFIG_FPGA_SPARTAN2
 355#define CONFIG_FPGA_SPARTAN3
 356
 357#define CONFIG_FPGA_COUNT       2
 358/*-----------------------------------------------------------------------
 359 * External Bus Controller (EBC) Setup
 360 *----------------------------------------------------------------------*/
 361
 362/*
 363 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 364 */
 365#define CONFIG_SYS_NAND_CS              2       /* NAND chip connected to CSx   */
 366
 367/* Memory Bank 0 (NOR-FLASH) initialization */
 368#define CONFIG_SYS_EBC_PB0AP            0x03017200
 369#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 370
 371/* Memory Bank 2 (NAND-FLASH) initialization */
 372#define CONFIG_SYS_EBC_PB2AP            0x018003c0
 373#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 374
 375/* Memory Bank 1 (RESET) initialization */
 376#define CONFIG_SYS_EBC_PB1AP            0x7f817200 /* 0x03017200 */
 377#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_RESET_BASE | 0x1c000)
 378
 379/* Memory Bank 4 (FPGA / 32Bit) initialization */
 380#define CONFIG_SYS_EBC_PB4AP            0x03840f40      /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
 381#define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_FPGA_BASE0 | 0x1c000)       /* BS=1M,BU=R/W,BW=32bit */
 382
 383/* Memory Bank 5 (FPGA / 16Bit) initialization */
 384#define CONFIG_SYS_EBC_PB5AP            0x03840f40      /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
 385#define CONFIG_SYS_EBC_PB5CR            (CONFIG_SYS_FPGA_BASE1 | 0x1a000)       /* BS=1M,BU=R/W,BW=16bit */
 386
 387/*-----------------------------------------------------------------------
 388 * NAND FLASH
 389 *----------------------------------------------------------------------*/
 390#define CONFIG_SYS_MAX_NAND_DEVICE      1
 391#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 392#define CONFIG_SYS_NAND_SELECT_DEVICE   1 /* nand driver supports mutipl. chips */
 393
 394#if defined(CONFIG_CMD_KGDB)
 395#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 396#endif
 397
 398#define CONFIG_API              1
 399
 400#endif /* __CONFIG_H */
 401