1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 21#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ 22#define CONFIG_DISPLAY_BOARDINFO 23 24#define CONFIG_SYS_TEXT_BASE 0x40000000 25 26#ifdef CONFIG_LCD /* with LCD controller ? */ 27#define CONFIG_MPC8XX_LCD 28/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ 29#endif 30 31#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 32#define CONFIG_SYS_SMC_RXBUFLEN 128 33#define CONFIG_SYS_MAXIDLE 10 34#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 35 36#define CONFIG_BOOTCOUNT_LIMIT 37 38 39#define CONFIG_BOARD_TYPES 1 /* support board types */ 40 41#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 42 43#undef CONFIG_BOOTARGS 44 45#define CONFIG_EXTRA_ENV_SETTINGS \ 46 "netdev=eth0\0" \ 47 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 48 "nfsroot=${serverip}:${rootpath}\0" \ 49 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 50 "addip=setenv bootargs ${bootargs} " \ 51 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 52 ":${hostname}:${netdev}:off panic=1\0" \ 53 "flash_nfs=run nfsargs addip;" \ 54 "bootm ${kernel_addr}\0" \ 55 "flash_self=run ramargs addip;" \ 56 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 57 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 58 "rootpath=/opt/eldk/ppc_8xx\0" \ 59 "hostname=TQM823M\0" \ 60 "bootfile=TQM823M/uImage\0" \ 61 "fdt_addr=40080000\0" \ 62 "kernel_addr=400A0000\0" \ 63 "ramdisk_addr=40280000\0" \ 64 "u-boot=TQM823M/u-image.bin\0" \ 65 "load=tftp 200000 ${u-boot}\0" \ 66 "update=prot off 40000000 +${filesize};" \ 67 "era 40000000 +${filesize};" \ 68 "cp.b 200000 40000000 ${filesize};" \ 69 "sete filesize;save\0" \ 70 "" 71#define CONFIG_BOOTCOMMAND "run flash_self" 72 73#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 74#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 75 76#undef CONFIG_WATCHDOG /* watchdog disabled */ 77 78#ifdef CONFIG_LCD 79# undef CONFIG_STATUS_LED /* disturbs display */ 80#else 81# define CONFIG_STATUS_LED 1 /* Status LED enabled */ 82#endif /* CONFIG_LCD */ 83 84#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 85 86/* 87 * BOOTP options 88 */ 89#define CONFIG_BOOTP_SUBNETMASK 90#define CONFIG_BOOTP_GATEWAY 91#define CONFIG_BOOTP_HOSTNAME 92#define CONFIG_BOOTP_BOOTPATH 93#define CONFIG_BOOTP_BOOTFILESIZE 94 95#define CONFIG_MAC_PARTITION 96#define CONFIG_DOS_PARTITION 97 98#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 99 100/* 101 * Command line configuration. 102 */ 103#define CONFIG_CMD_DATE 104#define CONFIG_CMD_IDE 105#define CONFIG_CMD_JFFS2 106 107#define CONFIG_NETCONSOLE 108 109/* 110 * Miscellaneous configurable options 111 */ 112#define CONFIG_SYS_LONGHELP /* undef to save memory */ 113 114#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 115 116#if defined(CONFIG_CMD_KGDB) 117#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 118#else 119#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 120#endif 121#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 122#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 123#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 124 125#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 126#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 127 128#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 129 130/* 131 * Low Level Configuration Settings 132 * (address mappings, register initial values, etc.) 133 * You should know what you are doing if you make changes here. 134 */ 135/*----------------------------------------------------------------------- 136 * Internal Memory Mapped Register 137 */ 138#define CONFIG_SYS_IMMR 0xFFF00000 139 140/*----------------------------------------------------------------------- 141 * Definitions for initial stack pointer and data area (in DPRAM) 142 */ 143#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 144#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 145#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 146#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 147 148/*----------------------------------------------------------------------- 149 * Start addresses for the final memory configuration 150 * (Set up by the startup code) 151 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 152 */ 153#define CONFIG_SYS_SDRAM_BASE 0x00000000 154#define CONFIG_SYS_FLASH_BASE 0x40000000 155#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 156#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 157#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 158 159/* 160 * For booting Linux, the board info and command line data 161 * have to be in the first 8 MB of memory, since this is 162 * the maximum mapped by the Linux kernel during initialization. 163 */ 164#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 165 166/*----------------------------------------------------------------------- 167 * FLASH organization 168 */ 169 170/* use CFI flash driver */ 171#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 172#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 173#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 174#define CONFIG_SYS_FLASH_EMPTY_INFO 175#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 176#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 177#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 178 179#define CONFIG_ENV_IS_IN_FLASH 1 180#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 181#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 182#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 183 184/* Address and size of Redundant Environment Sector */ 185#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 186#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 187 188#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 189 190#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 191 192/*----------------------------------------------------------------------- 193 * Dynamic MTD partition support 194 */ 195#define CONFIG_CMD_MTDPARTS 196#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 197#define CONFIG_FLASH_CFI_MTD 198#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 199 200#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 201 "128k(dtb)," \ 202 "1920k(kernel)," \ 203 "5632(rootfs)," \ 204 "4m(data)" 205 206/*----------------------------------------------------------------------- 207 * Hardware Information Block 208 */ 209#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 210#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 211#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 212 213/*----------------------------------------------------------------------- 214 * Cache Configuration 215 */ 216#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 217#if defined(CONFIG_CMD_KGDB) 218#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 219#endif 220 221/*----------------------------------------------------------------------- 222 * SYPCR - System Protection Control 11-9 223 * SYPCR can only be written once after reset! 224 *----------------------------------------------------------------------- 225 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 226 */ 227#if defined(CONFIG_WATCHDOG) 228#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 229 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 230#else 231#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 232#endif 233 234/*----------------------------------------------------------------------- 235 * SIUMCR - SIU Module Configuration 11-6 236 *----------------------------------------------------------------------- 237 * PCMCIA config., multi-function pin tri-state 238 */ 239#ifndef CONFIG_CAN_DRIVER 240#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 241#else /* we must activate GPL5 in the SIUMCR for CAN */ 242#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 243#endif /* CONFIG_CAN_DRIVER */ 244 245/*----------------------------------------------------------------------- 246 * TBSCR - Time Base Status and Control 11-26 247 *----------------------------------------------------------------------- 248 * Clear Reference Interrupt Status, Timebase freezing enabled 249 */ 250#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 251 252/*----------------------------------------------------------------------- 253 * RTCSC - Real-Time Clock Status and Control Register 11-27 254 *----------------------------------------------------------------------- 255 */ 256#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 257 258/*----------------------------------------------------------------------- 259 * PISCR - Periodic Interrupt Status and Control 11-31 260 *----------------------------------------------------------------------- 261 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 262 */ 263#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 264 265/*----------------------------------------------------------------------- 266 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 267 *----------------------------------------------------------------------- 268 * Reset PLL lock status sticky bit, timer expired status bit and timer 269 * interrupt status bit 270 */ 271#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 272 273/*----------------------------------------------------------------------- 274 * SCCR - System Clock and reset Control Register 15-27 275 *----------------------------------------------------------------------- 276 * Set clock output, timebase and RTC source and divider, 277 * power management and some other internal clocks 278 */ 279#define SCCR_MASK SCCR_EBDF11 280#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 281 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 282 SCCR_DFALCD00) 283 284/*----------------------------------------------------------------------- 285 * PCMCIA stuff 286 *----------------------------------------------------------------------- 287 * 288 */ 289#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 290#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 291#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 292#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 293#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 294#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 295#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 296#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 297 298/*----------------------------------------------------------------------- 299 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 300 *----------------------------------------------------------------------- 301 */ 302 303#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 304#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 305 306#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 307#undef CONFIG_IDE_LED /* LED for ide not supported */ 308#undef CONFIG_IDE_RESET /* reset for ide not supported */ 309 310#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 311#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 312 313#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 314 315#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 316 317/* Offset for data I/O */ 318#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 319 320/* Offset for normal register accesses */ 321#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 322 323/* Offset for alternate registers */ 324#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 325 326/*----------------------------------------------------------------------- 327 * 328 *----------------------------------------------------------------------- 329 * 330 */ 331#define CONFIG_SYS_DER 0 332 333/* 334 * Init Memory Controller: 335 * 336 * BR0/1 and OR0/1 (FLASH) 337 */ 338 339#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 340#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 341 342/* used to re-map FLASH both when starting from SRAM or FLASH: 343 * restrict access enough to keep SRAM working (if any) 344 * but not too much to meddle with FLASH accesses 345 */ 346#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 347#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 348 349/* 350 * FLASH timing: 351 */ 352#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 353 OR_SCY_3_CLK | OR_EHTR | OR_BI) 354 355#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 356#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 357#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 358 359#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 360#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 361#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 362 363/* 364 * BR2/3 and OR2/3 (SDRAM) 365 * 366 */ 367#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 368#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 369#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 370 371/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 372#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 373 374#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 375#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 376 377#ifndef CONFIG_CAN_DRIVER 378#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 379#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 380#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 381#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 382#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 383#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 384#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 385 BR_PS_8 | BR_MS_UPMB | BR_V ) 386#endif /* CONFIG_CAN_DRIVER */ 387 388/* 389 * Memory Periodic Timer Prescaler 390 * 391 * The Divider for PTA (refresh timer) configuration is based on an 392 * example SDRAM configuration (64 MBit, one bank). The adjustment to 393 * the number of chip selects (NCS) and the actually needed refresh 394 * rate is done by setting MPTPR. 395 * 396 * PTA is calculated from 397 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 398 * 399 * gclk CPU clock (not bus clock!) 400 * Trefresh Refresh cycle * 4 (four word bursts used) 401 * 402 * 4096 Rows from SDRAM example configuration 403 * 1000 factor s -> ms 404 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 405 * 4 Number of refresh cycles per period 406 * 64 Refresh cycle in ms per number of rows 407 * -------------------------------------------- 408 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 409 * 410 * 50 MHz => 50.000.000 / Divider = 98 411 * 66 Mhz => 66.000.000 / Divider = 129 412 * 80 Mhz => 80.000.000 / Divider = 156 413 */ 414 415#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 416#define CONFIG_SYS_MAMR_PTA 98 417 418/* 419 * For 16 MBit, refresh rates could be 31.3 us 420 * (= 64 ms / 2K = 125 / quad bursts). 421 * For a simpler initialization, 15.6 us is used instead. 422 * 423 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 424 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 425 */ 426#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 427#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 428 429/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 430#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 431#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 432 433/* 434 * MAMR settings for SDRAM 435 */ 436 437/* 8 column SDRAM */ 438#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 439 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 440 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 441/* 9 column SDRAM */ 442#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 443 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 444 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 445 446#define CONFIG_HWCONFIG 1 447 448#endif /* __CONFIG_H */ 449