1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ 21#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ 22#define CONFIG_DISPLAY_BOARDINFO 23 24#define CONFIG_SYS_TEXT_BASE 0x40000000 25 26#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 27#define CONFIG_SYS_SMC_RXBUFLEN 128 28#define CONFIG_SYS_MAXIDLE 10 29#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 30 31#define CONFIG_BOOTCOUNT_LIMIT 32 33 34#define CONFIG_BOARD_TYPES 1 /* support board types */ 35 36#define CONFIG_PREBOOT "echo;" \ 37 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 38 "echo" 39 40#undef CONFIG_BOOTARGS 41 42#define CONFIG_EXTRA_ENV_SETTINGS \ 43 "netdev=eth0\0" \ 44 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 45 "nfsroot=${serverip}:${rootpath}\0" \ 46 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 47 "addip=setenv bootargs ${bootargs} " \ 48 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 49 ":${hostname}:${netdev}:off panic=1\0" \ 50 "flash_nfs=run nfsargs addip;" \ 51 "bootm ${kernel_addr}\0" \ 52 "flash_self=run ramargs addip;" \ 53 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 54 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 55 "rootpath=/opt/eldk/ppc_8xx\0" \ 56 "hostname=TQM855M\0" \ 57 "bootfile=TQM855M/uImage\0" \ 58 "fdt_addr=40080000\0" \ 59 "kernel_addr=400A0000\0" \ 60 "ramdisk_addr=40280000\0" \ 61 "u-boot=TQM855M/u-image.bin\0" \ 62 "load=tftp 200000 ${u-boot}\0" \ 63 "update=prot off 40000000 +${filesize};" \ 64 "era 40000000 +${filesize};" \ 65 "cp.b 200000 40000000 ${filesize};" \ 66 "sete filesize;save\0" \ 67 "" 68#define CONFIG_BOOTCOMMAND "run flash_self" 69 70#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 71#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 72 73#undef CONFIG_WATCHDOG /* watchdog disabled */ 74 75#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 76 77#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 78 79/* enable I2C and select the hardware/software driver */ 80#define CONFIG_SYS_I2C 81#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 82#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ 83#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE 84/* 85 * Software (bit-bang) I2C driver configuration 86 */ 87#define PB_SCL 0x00000020 /* PB 26 */ 88#define PB_SDA 0x00000010 /* PB 27 */ 89 90#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 91#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 92#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 93#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 94#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 95 else immr->im_cpm.cp_pbdat &= ~PB_SDA 96#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 97 else immr->im_cpm.cp_pbdat &= ~PB_SCL 98#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 99 100#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ 101#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ 102#if 0 103#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ 104#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 105#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 106#endif 107 108/* 109 * BOOTP options 110 */ 111#define CONFIG_BOOTP_SUBNETMASK 112#define CONFIG_BOOTP_GATEWAY 113#define CONFIG_BOOTP_HOSTNAME 114#define CONFIG_BOOTP_BOOTPATH 115#define CONFIG_BOOTP_BOOTFILESIZE 116 117#define CONFIG_MAC_PARTITION 118#define CONFIG_DOS_PARTITION 119 120#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 121 122/* 123 * Command line configuration. 124 */ 125#define CONFIG_CMD_DATE 126#define CONFIG_CMD_EEPROM 127#define CONFIG_CMD_IDE 128#define CONFIG_CMD_JFFS2 129 130#define CONFIG_NETCONSOLE 131 132/* 133 * Miscellaneous configurable options 134 */ 135#define CONFIG_SYS_LONGHELP /* undef to save memory */ 136 137#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 138 139#if defined(CONFIG_CMD_KGDB) 140#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 141#else 142#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 143#endif 144#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 145#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 146#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 147 148#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 149#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 150 151#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 152 153/* 154 * Low Level Configuration Settings 155 * (address mappings, register initial values, etc.) 156 * You should know what you are doing if you make changes here. 157 */ 158/*----------------------------------------------------------------------- 159 * Internal Memory Mapped Register 160 */ 161#define CONFIG_SYS_IMMR 0xFFF00000 162 163/*----------------------------------------------------------------------- 164 * Definitions for initial stack pointer and data area (in DPRAM) 165 */ 166#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 167#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 168#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 169#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 170 171/*----------------------------------------------------------------------- 172 * Start addresses for the final memory configuration 173 * (Set up by the startup code) 174 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 175 */ 176#define CONFIG_SYS_SDRAM_BASE 0x00000000 177#define CONFIG_SYS_FLASH_BASE 0x40000000 178#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 179#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 180#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 181 182/* 183 * For booting Linux, the board info and command line data 184 * have to be in the first 8 MB of memory, since this is 185 * the maximum mapped by the Linux kernel during initialization. 186 */ 187#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 188 189/*----------------------------------------------------------------------- 190 * FLASH organization 191 */ 192 193/* use CFI flash driver */ 194#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 195#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 196#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 197#define CONFIG_SYS_FLASH_EMPTY_INFO 198#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 199#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 200#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 201 202#define CONFIG_ENV_IS_IN_FLASH 1 203#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 204#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 205#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ 206 207/* Address and size of Redundant Environment Sector */ 208#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 209#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 210 211#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 212 213#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 214 215/*----------------------------------------------------------------------- 216 * Dynamic MTD partition support 217 */ 218#define CONFIG_CMD_MTDPARTS 219#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 220#define CONFIG_FLASH_CFI_MTD 221#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 222 223#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 224 "128k(dtb)," \ 225 "1920k(kernel)," \ 226 "5632(rootfs)," \ 227 "4m(data)" 228 229/*----------------------------------------------------------------------- 230 * Hardware Information Block 231 */ 232#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 233#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 234#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 235 236/*----------------------------------------------------------------------- 237 * Cache Configuration 238 */ 239#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 240#if defined(CONFIG_CMD_KGDB) 241#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 242#endif 243 244/*----------------------------------------------------------------------- 245 * SYPCR - System Protection Control 11-9 246 * SYPCR can only be written once after reset! 247 *----------------------------------------------------------------------- 248 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 249 */ 250#if defined(CONFIG_WATCHDOG) 251#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 252 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 253#else 254#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 255#endif 256 257/*----------------------------------------------------------------------- 258 * SIUMCR - SIU Module Configuration 11-6 259 *----------------------------------------------------------------------- 260 * PCMCIA config., multi-function pin tri-state 261 */ 262#ifndef CONFIG_CAN_DRIVER 263#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 264#else /* we must activate GPL5 in the SIUMCR for CAN */ 265#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 266#endif /* CONFIG_CAN_DRIVER */ 267 268/*----------------------------------------------------------------------- 269 * TBSCR - Time Base Status and Control 11-26 270 *----------------------------------------------------------------------- 271 * Clear Reference Interrupt Status, Timebase freezing enabled 272 */ 273#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 274 275/*----------------------------------------------------------------------- 276 * RTCSC - Real-Time Clock Status and Control Register 11-27 277 *----------------------------------------------------------------------- 278 */ 279#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 280 281/*----------------------------------------------------------------------- 282 * PISCR - Periodic Interrupt Status and Control 11-31 283 *----------------------------------------------------------------------- 284 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 285 */ 286#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 287 288/*----------------------------------------------------------------------- 289 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 290 *----------------------------------------------------------------------- 291 * Reset PLL lock status sticky bit, timer expired status bit and timer 292 * interrupt status bit 293 */ 294#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 295 296/*----------------------------------------------------------------------- 297 * SCCR - System Clock and reset Control Register 15-27 298 *----------------------------------------------------------------------- 299 * Set clock output, timebase and RTC source and divider, 300 * power management and some other internal clocks 301 */ 302#define SCCR_MASK SCCR_EBDF11 303#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 304 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 305 SCCR_DFALCD00) 306 307/*----------------------------------------------------------------------- 308 * PCMCIA stuff 309 *----------------------------------------------------------------------- 310 * 311 */ 312#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 313#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 314#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 315#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 316#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 317#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 318#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 319#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 320 321/*----------------------------------------------------------------------- 322 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 323 *----------------------------------------------------------------------- 324 */ 325 326#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 327#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 328 329#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 330#undef CONFIG_IDE_LED /* LED for ide not supported */ 331#undef CONFIG_IDE_RESET /* reset for ide not supported */ 332 333#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 334#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 335 336#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 337 338#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 339 340/* Offset for data I/O */ 341#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 342 343/* Offset for normal register accesses */ 344#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 345 346/* Offset for alternate registers */ 347#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 348 349/*----------------------------------------------------------------------- 350 * 351 *----------------------------------------------------------------------- 352 * 353 */ 354#define CONFIG_SYS_DER 0 355 356/* 357 * Init Memory Controller: 358 * 359 * BR0/1 and OR0/1 (FLASH) 360 */ 361 362#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 363#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 364 365/* used to re-map FLASH both when starting from SRAM or FLASH: 366 * restrict access enough to keep SRAM working (if any) 367 * but not too much to meddle with FLASH accesses 368 */ 369#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 370#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 371 372/* 373 * FLASH timing: 374 */ 375#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 376 OR_SCY_3_CLK | OR_EHTR | OR_BI) 377 378#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 379#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 380#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 381 382#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 383#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 384#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 385 386/* 387 * BR2/3 and OR2/3 (SDRAM) 388 * 389 */ 390#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 391#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 392#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 393 394/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 395#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 396 397#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 398#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 399 400#ifndef CONFIG_CAN_DRIVER 401#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 402#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 403#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 404#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 405#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 406#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 407#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 408 BR_PS_8 | BR_MS_UPMB | BR_V ) 409#endif /* CONFIG_CAN_DRIVER */ 410 411/* 412 * Memory Periodic Timer Prescaler 413 * 414 * The Divider for PTA (refresh timer) configuration is based on an 415 * example SDRAM configuration (64 MBit, one bank). The adjustment to 416 * the number of chip selects (NCS) and the actually needed refresh 417 * rate is done by setting MPTPR. 418 * 419 * PTA is calculated from 420 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 421 * 422 * gclk CPU clock (not bus clock!) 423 * Trefresh Refresh cycle * 4 (four word bursts used) 424 * 425 * 4096 Rows from SDRAM example configuration 426 * 1000 factor s -> ms 427 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 428 * 4 Number of refresh cycles per period 429 * 64 Refresh cycle in ms per number of rows 430 * -------------------------------------------- 431 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 432 * 433 * 50 MHz => 50.000.000 / Divider = 98 434 * 66 Mhz => 66.000.000 / Divider = 129 435 * 80 Mhz => 80.000.000 / Divider = 156 436 */ 437 438#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 439#define CONFIG_SYS_MAMR_PTA 98 440 441/* 442 * For 16 MBit, refresh rates could be 31.3 us 443 * (= 64 ms / 2K = 125 / quad bursts). 444 * For a simpler initialization, 15.6 us is used instead. 445 * 446 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 447 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 448 */ 449#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 450#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 451 452/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 453#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 454#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 455 456/* 457 * MAMR settings for SDRAM 458 */ 459 460/* 8 column SDRAM */ 461#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 462 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 463 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 464/* 9 column SDRAM */ 465#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 466 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 467 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 468 469#define CONFIG_SCC1_ENET 470#define CONFIG_FEC_ENET 471#define CONFIG_ETHPRIME "SCC" 472 473#define CONFIG_HWCONFIG 1 474 475#endif /* __CONFIG_H */ 476