1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ 21#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ 22#define CONFIG_DISPLAY_BOARDINFO 23 24#define CONFIG_SYS_TEXT_BASE 0x40000000 25 26#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 27#define CONFIG_SYS_SMC_RXBUFLEN 128 28#define CONFIG_SYS_MAXIDLE 10 29#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 30 31#define CONFIG_BOOTCOUNT_LIMIT 32 33 34#define CONFIG_BOARD_TYPES 1 /* support board types */ 35 36#define CONFIG_PREBOOT "echo;" \ 37 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 38 "echo" 39 40#undef CONFIG_BOOTARGS 41 42#define CONFIG_EXTRA_ENV_SETTINGS \ 43 "netdev=eth0\0" \ 44 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 45 "nfsroot=${serverip}:${rootpath}\0" \ 46 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 47 "addip=setenv bootargs ${bootargs} " \ 48 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 49 ":${hostname}:${netdev}:off panic=1\0" \ 50 "flash_nfs=run nfsargs addip;" \ 51 "bootm ${kernel_addr}\0" \ 52 "flash_self=run ramargs addip;" \ 53 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 54 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 55 "rootpath=/opt/eldk/ppc_8xx\0" \ 56 "hostname=TQM860M\0" \ 57 "bootfile=TQM860M/uImage\0" \ 58 "fdt_addr=400C0000\0" \ 59 "kernel_addr=40100000\0" \ 60 "ramdisk_addr=40280000\0" \ 61 "u-boot=TQM860M/u-image.bin\0" \ 62 "load=tftp 200000 ${u-boot}\0" \ 63 "update=prot off 40000000 +${filesize};" \ 64 "era 40000000 +${filesize};" \ 65 "cp.b 200000 40000000 ${filesize};" \ 66 "sete filesize;save\0" \ 67 "" 68#define CONFIG_BOOTCOMMAND "run flash_self" 69 70#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 71#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 72 73#undef CONFIG_WATCHDOG /* watchdog disabled */ 74 75#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 76 77#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 78 79/* 80 * BOOTP options 81 */ 82#define CONFIG_BOOTP_SUBNETMASK 83#define CONFIG_BOOTP_GATEWAY 84#define CONFIG_BOOTP_HOSTNAME 85#define CONFIG_BOOTP_BOOTPATH 86#define CONFIG_BOOTP_BOOTFILESIZE 87 88#define CONFIG_MAC_PARTITION 89#define CONFIG_DOS_PARTITION 90 91#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 92 93/* 94 * Command line configuration. 95 */ 96#define CONFIG_CMD_DATE 97#define CONFIG_CMD_IDE 98#define CONFIG_CMD_JFFS2 99 100#define CONFIG_NETCONSOLE 101 102/* 103 * Miscellaneous configurable options 104 */ 105#define CONFIG_SYS_LONGHELP /* undef to save memory */ 106 107#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 108 109#if defined(CONFIG_CMD_KGDB) 110#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 111#else 112#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 113#endif 114#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 115#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 116#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 117 118#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 119#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 120 121#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 122 123/* 124 * Low Level Configuration Settings 125 * (address mappings, register initial values, etc.) 126 * You should know what you are doing if you make changes here. 127 */ 128/*----------------------------------------------------------------------- 129 * Internal Memory Mapped Register 130 */ 131#define CONFIG_SYS_IMMR 0xFFF00000 132 133/*----------------------------------------------------------------------- 134 * Definitions for initial stack pointer and data area (in DPRAM) 135 */ 136#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 137#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 138#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 139#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 140 141/*----------------------------------------------------------------------- 142 * Start addresses for the final memory configuration 143 * (Set up by the startup code) 144 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 145 */ 146#define CONFIG_SYS_SDRAM_BASE 0x00000000 147#define CONFIG_SYS_FLASH_BASE 0x40000000 148#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 149#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 150#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ 151 152/* 153 * For booting Linux, the board info and command line data 154 * have to be in the first 8 MB of memory, since this is 155 * the maximum mapped by the Linux kernel during initialization. 156 */ 157#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 158 159/*----------------------------------------------------------------------- 160 * FLASH organization 161 */ 162/* use CFI flash driver */ 163#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 164#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 165#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 166#define CONFIG_SYS_FLASH_EMPTY_INFO 167#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 168#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 169#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 170 171#define CONFIG_ENV_IS_IN_FLASH 1 172#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 173#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ 174#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 175 176/* Address and size of Redundant Environment Sector */ 177#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 178#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 179 180#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 181 182#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 183 184/*----------------------------------------------------------------------- 185 * Dynamic MTD partition support 186 */ 187#define CONFIG_CMD_MTDPARTS 188#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 189#define CONFIG_FLASH_CFI_MTD 190#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 191 192#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 193 "128k(dtb)," \ 194 "1920k(kernel)," \ 195 "5632(rootfs)," \ 196 "4m(data)" 197 198/*----------------------------------------------------------------------- 199 * Hardware Information Block 200 */ 201#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 202#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 203#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 204 205/*----------------------------------------------------------------------- 206 * Cache Configuration 207 */ 208#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 209#if defined(CONFIG_CMD_KGDB) 210#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 211#endif 212 213/*----------------------------------------------------------------------- 214 * SYPCR - System Protection Control 11-9 215 * SYPCR can only be written once after reset! 216 *----------------------------------------------------------------------- 217 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 218 */ 219#if defined(CONFIG_WATCHDOG) 220#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 221 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 222#else 223#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 224#endif 225 226/*----------------------------------------------------------------------- 227 * SIUMCR - SIU Module Configuration 11-6 228 *----------------------------------------------------------------------- 229 * PCMCIA config., multi-function pin tri-state 230 */ 231#ifndef CONFIG_CAN_DRIVER 232#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 233#else /* we must activate GPL5 in the SIUMCR for CAN */ 234#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 235#endif /* CONFIG_CAN_DRIVER */ 236 237/*----------------------------------------------------------------------- 238 * TBSCR - Time Base Status and Control 11-26 239 *----------------------------------------------------------------------- 240 * Clear Reference Interrupt Status, Timebase freezing enabled 241 */ 242#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 243 244/*----------------------------------------------------------------------- 245 * RTCSC - Real-Time Clock Status and Control Register 11-27 246 *----------------------------------------------------------------------- 247 */ 248#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 249 250/*----------------------------------------------------------------------- 251 * PISCR - Periodic Interrupt Status and Control 11-31 252 *----------------------------------------------------------------------- 253 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 254 */ 255#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 256 257/*----------------------------------------------------------------------- 258 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 259 *----------------------------------------------------------------------- 260 * Reset PLL lock status sticky bit, timer expired status bit and timer 261 * interrupt status bit 262 */ 263#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 264 265/*----------------------------------------------------------------------- 266 * SCCR - System Clock and reset Control Register 15-27 267 *----------------------------------------------------------------------- 268 * Set clock output, timebase and RTC source and divider, 269 * power management and some other internal clocks 270 */ 271#define SCCR_MASK SCCR_EBDF11 272#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 273 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 274 SCCR_DFALCD00) 275 276/*----------------------------------------------------------------------- 277 * PCMCIA stuff 278 *----------------------------------------------------------------------- 279 * 280 */ 281#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 282#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 283#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 284#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 285#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 286#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 287#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 288#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 289 290/*----------------------------------------------------------------------- 291 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 292 *----------------------------------------------------------------------- 293 */ 294 295#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 296#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 297 298#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 299#undef CONFIG_IDE_LED /* LED for ide not supported */ 300#undef CONFIG_IDE_RESET /* reset for ide not supported */ 301 302#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 303#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 304 305#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 306 307#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 308 309/* Offset for data I/O */ 310#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 311 312/* Offset for normal register accesses */ 313#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 314 315/* Offset for alternate registers */ 316#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 317 318/*----------------------------------------------------------------------- 319 * 320 *----------------------------------------------------------------------- 321 * 322 */ 323#define CONFIG_SYS_DER 0 324 325/* 326 * Init Memory Controller: 327 * 328 * BR0/1 and OR0/1 (FLASH) 329 */ 330 331#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 332#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 333 334/* used to re-map FLASH both when starting from SRAM or FLASH: 335 * restrict access enough to keep SRAM working (if any) 336 * but not too much to meddle with FLASH accesses 337 */ 338#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 339#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 340 341/* 342 * FLASH timing: 343 */ 344#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 345 OR_SCY_3_CLK | OR_EHTR | OR_BI) 346 347#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 348#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 349#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 350 351#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 352#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 353#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 354 355/* 356 * BR2/3 and OR2/3 (SDRAM) 357 * 358 */ 359#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 360#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 361#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */ 362 363/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 364#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 365 366#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 367#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 368 369#ifndef CONFIG_CAN_DRIVER 370#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 371#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 372#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 373#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 374#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 375#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 376#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 377 BR_PS_8 | BR_MS_UPMB | BR_V ) 378#endif /* CONFIG_CAN_DRIVER */ 379 380/* 381 * Memory Periodic Timer Prescaler 382 * 383 * The Divider for PTA (refresh timer) configuration is based on an 384 * example SDRAM configuration (64 MBit, one bank). The adjustment to 385 * the number of chip selects (NCS) and the actually needed refresh 386 * rate is done by setting MPTPR. 387 * 388 * PTA is calculated from 389 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 390 * 391 * gclk CPU clock (not bus clock!) 392 * Trefresh Refresh cycle * 4 (four word bursts used) 393 * 394 * 4096 Rows from SDRAM example configuration 395 * 1000 factor s -> ms 396 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 397 * 4 Number of refresh cycles per period 398 * 64 Refresh cycle in ms per number of rows 399 * -------------------------------------------- 400 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 401 * 402 * 50 MHz => 50.000.000 / Divider = 98 403 * 66 Mhz => 66.000.000 / Divider = 129 404 * 80 Mhz => 80.000.000 / Divider = 156 405 */ 406 407#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 408#define CONFIG_SYS_MAMR_PTA 98 409 410/* 411 * For 16 MBit, refresh rates could be 31.3 us 412 * (= 64 ms / 2K = 125 / quad bursts). 413 * For a simpler initialization, 15.6 us is used instead. 414 * 415 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 416 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 417 */ 418#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 419#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 420 421/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 422#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 423#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 424 425/* 426 * MAMR settings for SDRAM 427 */ 428 429/* 8 column SDRAM */ 430#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 431 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 432 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 433/* 9 column SDRAM */ 434#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 435 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 436 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 437/* 10 column SDRAM */ 438#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 439 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ 440 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 441 442#define CONFIG_SCC1_ENET 443#define CONFIG_FEC_ENET 444#define CONFIG_ETHPRIME "SCC" 445 446#define CONFIG_HWCONFIG 1 447 448#endif /* __CONFIG_H */ 449