1/* 2 * Copyright (C) 2006 Atmel Corporation 3 * 4 * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org> 5 * 6 * Configuration settings for the AVR32 Network Gateway 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10#ifndef __CONFIG_H 11#define __CONFIG_H 12 13#include <asm/arch/hardware.h> 14 15#define CONFIG_AT32AP 16#define CONFIG_AT32AP7000 17#define CONFIG_ATNGW100MKII 18 19#define CONFIG_BOARD_EARLY_INIT_F 20#define CONFIG_BOARD_EARLY_INIT_R 21 22/* 23 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL 24 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency 25 * and the PBA bus to run at 1/4 the PLL frequency. 26 */ 27#define CONFIG_PLL 28#define CONFIG_SYS_POWER_MANAGER 29#define CONFIG_SYS_OSC0_HZ 20000000 30#define CONFIG_SYS_PLL0_DIV 1 31#define CONFIG_SYS_PLL0_MUL 7 32#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 33/* 34 * Set the CPU running at: 35 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz 36 */ 37#define CONFIG_SYS_CLKDIV_CPU 0 38/* 39 * Set the HSB running at: 40 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz 41 */ 42#define CONFIG_SYS_CLKDIV_HSB 1 43/* 44 * Set the PBA running at: 45 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz 46 */ 47#define CONFIG_SYS_CLKDIV_PBA 2 48/* 49 * Set the PBB running at: 50 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz 51 */ 52#define CONFIG_SYS_CLKDIV_PBB 1 53 54/* Reserve VM regions for NOR flash, NAND flash and SDRAM */ 55#define CONFIG_SYS_NR_VM_REGIONS 3 56 57/* 58 * The PLLOPT register controls the PLL like this: 59 * icp = PLLOPT<2> 60 * ivco = PLLOPT<1:0> 61 * 62 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). 63 */ 64#define CONFIG_SYS_PLL0_OPT 0x04 65 66#define CONFIG_USART_BASE ATMEL_BASE_USART1 67#define CONFIG_USART_ID 1 68 69/* User serviceable stuff */ 70#define CONFIG_DOS_PARTITION 71 72#define CONFIG_CMDLINE_TAG 73#define CONFIG_SETUP_MEMORY_TAGS 74#define CONFIG_INITRD_TAG 75 76#define CONFIG_STACKSIZE (2048) 77 78#define CONFIG_BAUDRATE 115200 79#define CONFIG_BOOTARGS \ 80 "root=mtd:main rootfstype=jffs2" 81#define CONFIG_BOOTCOMMAND \ 82 "fsload 0x10400000 /uImage; bootm" 83 84 85/* 86 * After booting the board for the first time, new ethernet addresses 87 * should be generated and assigned to the environment variables 88 * "ethaddr" and "eth1addr". This is normally done during production. 89 */ 90#define CONFIG_OVERWRITE_ETHADDR_ONCE 91 92/* 93 * BOOTP/DHCP options 94 */ 95#define CONFIG_BOOTP_SUBNETMASK 96#define CONFIG_BOOTP_GATEWAY 97 98/* 99 * Command line configuration. 100 */ 101#define CONFIG_CMD_JFFS2 102 103#define CONFIG_ATMEL_USART 104#define CONFIG_MACB 105#define CONFIG_PORTMUX_PIO 106#define CONFIG_SYS_NR_PIOS 5 107#define CONFIG_SYS_HSDRAMC 108#define CONFIG_MMC 109#define CONFIG_GENERIC_ATMEL_MCI 110#define CONFIG_GENERIC_MMC 111#define CONFIG_ATMEL_SPI 112 113#define CONFIG_SYS_DCACHE_LINESZ 32 114#define CONFIG_SYS_ICACHE_LINESZ 32 115 116#define CONFIG_NR_DRAM_BANKS 1 117 118#define CONFIG_SYS_FLASH_CFI 119#define CONFIG_FLASH_CFI_DRIVER 120#define CONFIG_SYS_FLASH_PROTECTION 121 122#define CONFIG_SYS_FLASH_BASE 0x00000000 123#define CONFIG_SYS_FLASH_SIZE 0x800000 124#define CONFIG_SYS_MAX_FLASH_BANKS 1 125#define CONFIG_SYS_MAX_FLASH_SECT 135 126 127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 128#define CONFIG_SYS_TEXT_BASE 0x00000000 129 130#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE 131#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE 132#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE 133 134#define CONFIG_ENV_IS_IN_FLASH 135#define CONFIG_ENV_SIZE 65536 136#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) 137 138#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) 139 140#define CONFIG_SYS_MALLOC_LEN (256*1024) 141 142/* Allow 4MB for the kernel run-time image */ 143#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) 144#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) 145 146/* Other configuration settings that shouldn't have to change all that often */ 147#define CONFIG_SYS_CBSIZE 256 148#define CONFIG_SYS_MAXARGS 16 149#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 150#define CONFIG_SYS_LONGHELP 151 152#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 153#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) 154 155#define CONFIG_MTD_DEVICE 156#define CONFIG_MTD_PARTITIONS 157 158#endif /* __CONFIG_H */ 159