LXR uboot/include/configs/omap3

   1/*
   2 * Configuration settings for the QUIPOS Cairo board.
   3 *
   4 * Copyright (C) DENX GmbH
   5 *
   6 * Author :
   7 *      Albert ARIBAUD <albert.aribaud@3adev.fr>
   8 *
   9 * Derived from EVM  code by
  10 *      Manikandan Pillai <mani.pillai@ti.com>
  11 * Itself derived from Beagle Board and 3430 SDP code by
  12 *      Richard Woodruff <r-woodruff2@ti.com>
  13 *      Syed Mohammed Khasim <khasim@ti.com>
  14 *
  15 * Also derived from include/configs/omap3_beagle.h
  16 *
  17 * SPDX-License-Identifier:     GPL-2.0+
  18 */
  19
  20#ifndef __OMAP3_CAIRO_CONFIG_H
  21#define __OMAP3_CAIRO_CONFIG_H
  22
  23#define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
  24
  25/*
  26 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  27 * 64 bytes before this address should be set aside for u-boot.img's
  28 * header. That is 0x800FFFC0--0x80100000 should not be used for any
  29 * other needs.  We use this rather than the inherited defines from
  30 * ti_armv7_common.h for backwards compatibility.
  31 */
  32#define CONFIG_SYS_TEXT_BASE            0x80100000
  33#define CONFIG_SYS_UBOOT_START          CONFIG_SYS_TEXT_BASE
  34#define CONFIG_SPL_BSS_START_ADDR       0x80000000
  35#define CONFIG_SPL_BSS_MAX_SIZE         (512 << 10)     /* 512 KB */
  36#define CONFIG_SYS_SPL_MALLOC_START     0x80208000
  37#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  38
  39#define CONFIG_NAND
  40
  41#include <configs/ti_omap3_common.h>
  42
  43/*
  44 * Display CPU and Board information
  45 */
  46#define CONFIG_DISPLAY_CPUINFO          1
  47#define CONFIG_DISPLAY_BOARDINFO        1
  48
  49#define CONFIG_MISC_INIT_R
  50
  51#define CONFIG_REVISION_TAG             1
  52#define CONFIG_ENV_OVERWRITE
  53
  54/* Enable Multi Bus support for I2C */
  55#define CONFIG_I2C_MULTI_BUS            1
  56
  57/* Probe all devices */
  58#define CONFIG_SYS_I2C_NOPROBES         { {0x0, 0x0} }
  59
  60#define CONFIG_NAND
  61
  62/* commands to include */
  63#define CONFIG_CMD_NAND_LOCK_UNLOCK
  64
  65/*
  66 * TWL4030
  67 */
  68#define CONFIG_TWL4030_LED              1
  69
  70/*
  71 * Board NAND Info.
  72 */
  73#define CONFIG_NAND_OMAP_GPMC
  74#define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
  75                                                        /* devices */
  76#define CONFIG_EXTRA_ENV_SETTINGS \
  77        "machid=ffffffff\0" \
  78        "fdt_high=0x87000000\0" \
  79        "baudrate=115200\0" \
  80        "fec_addr=00:50:C2:7E:90:F0\0" \
  81        "netmask=255.255.255.0\0" \
  82        "ipaddr=192.168.2.9\0" \
  83        "gateway=192.168.2.1\0" \
  84        "serverip=192.168.2.10\0" \
  85        "nfshost=192.168.2.10\0" \
  86        "stdin=serial\0" \
  87        "stdout=serial\0" \
  88        "stderr=serial\0" \
  89        "bootargs_mmc_ramdisk=mem=128M " \
  90                "console=ttyO1,115200n8 " \
  91                "root=/dev/ram0 rw " \
  92                "initrd=0x81600000,16M " \
  93                "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
  94                "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
  95        "mmcboot=mmc init; " \
  96                "fatload mmc 0 0x80000000 uImage; " \
  97                "fatload mmc 0 0x81600000 ramdisk.gz; " \
  98                "setenv bootargs ${bootargs_mmc_ramdisk}; " \
  99                "bootm 0x80000000\0" \
 100        "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
 101        "root=/dev/nfs " \
 102        "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
 103        "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
 104        "omap_vout.vid1_static_vrfb_alloc=y\0" \
 105        "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
 106        "bootm 0x80000000\0" \
 107        "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
 108        "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
 109        "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
 110        "omapfb.rotate_type=1\0" \
 111        "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
 112        "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
 113        "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
 114        "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
 115        "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
 116        "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
 117        "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
 118        "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
 119        "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
 120        "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
 121        "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
 122        "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
 123        "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
 124        "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
 125        "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
 126                "nand erase 0 20000; " \
 127                "fatload mmc 0 0x81600000 MLO; " \
 128                "nandecc hw; " \
 129                "nand write.i 0x81600000 0 20000;\0" \
 130        "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
 131                "nand erase 80000 40000; " \
 132                "fatload mmc 0 0x81600000 u-boot.bin; " \
 133                "nandecc sw; " \
 134                "nand write.i 0x81600000 80000 40000;\0" \
 135        "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
 136                "nand erase 280000 300000; " \
 137                "fatload mmc 0 0x81600000 uImage; " \
 138                "nandecc sw; " \
 139                "nand write.i 0x81600000 280000 300000;\0" \
 140        "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
 141                "nandecc sw; " \
 142                "nand write.jffs2 0x680000 0xFF ${filesize}; " \
 143                "nand erase 680000 ${filesize}; " \
 144                "nand write.jffs2 81600000 680000 ${filesize};\0" \
 145        "flash_scrub=nand scrub; " \
 146                "run flash_xloader; " \
 147                "run flash_uboot; " \
 148                "run flash_kernel; " \
 149                "run flash_rootfs;\0" \
 150        "flash_all=run ledred; " \
 151                "nand erase.chip; " \
 152                "run ledorange; " \
 153                "run flash_xloader; " \
 154                "run flash_uboot; " \
 155                "run flash_kernel; " \
 156                "run flash_rootfs; " \
 157                "run ledgreen; " \
 158                "run boot_nand; \0" \
 159
 160#define CONFIG_BOOTCOMMAND \
 161        "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
 162        "else run boot_nand; fi"
 163
 164/*
 165 * OMAP3 has 12 GP timers, they can be driven by the system clock
 166 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 167 * This rate is divided by a local divisor.
 168 */
 169#define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 170
 171/*-----------------------------------------------------------------------
 172 * FLASH and environment organization
 173 */
 174
 175/* **** PISMO SUPPORT *** */
 176#if defined(CONFIG_CMD_NAND)
 177#define CONFIG_SYS_FLASH_BASE           NAND_BASE
 178#endif
 179
 180/* Monitor at start of flash */
 181#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 182#define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 183
 184#define CONFIG_ENV_IS_IN_NAND           1
 185#define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
 186#define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 187#define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 188
 189#define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB */
 190#define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 191#define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 192
 193#define CONFIG_OMAP3_SPI
 194
 195/* Defines for SPL */
 196#define CONFIG_SPL_OMAP3_ID_NAND
 197
 198/* NAND boot config */
 199#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 200#define CONFIG_SYS_NAND_PAGE_COUNT      64
 201#define CONFIG_SYS_NAND_PAGE_SIZE       2048
 202#define CONFIG_SYS_NAND_OOBSIZE         64
 203#define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 204#define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 205#define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 206                                                10, 11, 12, 13}
 207#define CONFIG_SYS_NAND_ECCSIZE         512
 208#define CONFIG_SYS_NAND_ECCBYTES        3
 209#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 210#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 211/* NAND: SPL falcon mode configs */
 212#ifdef CONFIG_SPL_OS_BOOT
 213#define CONFIG_CMD_SPL_NAND_OFS         0x240000
 214#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
 215#define CONFIG_CMD_SPL_WRITE_SIZE       0x2000
 216#endif
 217
 218/* env defaults */
 219#define CONFIG_BOOTFILE                 "uImage"
 220
 221/* Override OMAP3 common serial console configuration from UART3
 222 * to UART2.
 223 *
 224 * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
 225 * are needed and peripheral clocks for UART2 must be enabled in
 226 * function per_clocks_enable().
 227 */
 228#undef CONFIG_CONS_INDEX
 229#define CONFIG_CONS_INDEX               2
 230#ifdef CONFIG_SPL_BUILD
 231#undef CONFIG_SYS_NS16550_COM3
 232#define CONFIG_SYS_NS16550_COM2         OMAP34XX_UART2
 233#undef CONFIG_SERIAL3
 234#define CONFIG_SERIAL2
 235#endif
 236
 237/* Provide MACH_TYPE for compatibility with non-DT kernels */
 238#define MACH_TYPE_OMAP3_CAIRO   3063
 239#define CONFIG_MACH_TYPE        MACH_TYPE_OMAP3_CAIRO
 240
 241/*-----------------------------------------------------------------------
 242 * FLASH and environment organization
 243 */
 244
 245/* **** PISMO SUPPORT *** */
 246
 247#define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors */
 248                                                /* on one chip */
 249#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 250
 251/*-----------------------------------------------------------------------
 252 * CFI FLASH driver setup
 253 */
 254/* timeout values are in ticks */
 255#define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 256#define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 257
 258/* Flash banks JFFS2 should use */
 259#define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 260                                        CONFIG_SYS_MAX_NAND_DEVICE)
 261#define CONFIG_SYS_JFFS2_MEM_NAND
 262/* use flash_info[2] */
 263#define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 264#define CONFIG_SYS_JFFS2_NUM_BANKS      1
 265
 266#endif /* __OMAP3_CAIRO_CONFIG_H */
 267