1/* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2014 Bachmann electronic GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef __CONFIG_H 9#define __CONFIG_H 10 11#include "mx6_common.h" 12 13/* Size of malloc() pool */ 14#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 15 16#define CONFIG_BOARD_EARLY_INIT_F 17#define CONFIG_MISC_INIT_R 18 19/* UART Configs */ 20#define CONFIG_MXC_UART 21#define CONFIG_MXC_UART_BASE UART1_BASE 22 23/* SF Configs */ 24#define CONFIG_SPI 25#define CONFIG_MXC_SPI 26#define CONFIG_SF_DEFAULT_BUS 2 27#define CONFIG_SF_DEFAULT_CS 0 28#define CONFIG_SF_DEFAULT_SPEED 25000000 29#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 30 31/* IO expander */ 32#define CONFIG_PCA953X 33#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 34#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } 35#define CONFIG_CMD_PCA953X 36#define CONFIG_CMD_PCA953X_INFO 37 38/* I2C Configs */ 39#define CONFIG_SYS_I2C 40#define CONFIG_SYS_I2C_MXC 41#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 42#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 43#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 44#define CONFIG_SYS_I2C_SPEED 100000 45 46/* OCOTP Configs */ 47#define CONFIG_CMD_IMXOTP 48#define CONFIG_IMX_OTP 49#define IMX_OTP_BASE OCOTP_BASE_ADDR 50#define IMX_OTP_ADDR_MAX 0x7F 51#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA 52#define IMX_OTPWRITE_ENABLED 53 54/* MMC Configs */ 55#define CONFIG_SYS_FSL_ESDHC_ADDR 0 56#define CONFIG_SYS_FSL_USDHC_NUM 2 57 58/* USB Configs */ 59#define CONFIG_USB_EHCI 60#define CONFIG_USB_EHCI_MX6 61#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 62#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 63 64#ifdef CONFIG_MX6Q 65#define CONFIG_CMD_SATA 66#endif 67 68/* 69 * SATA Configs 70 */ 71#ifdef CONFIG_CMD_SATA 72#define CONFIG_DWC_AHSATA 73#define CONFIG_SYS_SATA_MAX_DEVICE 1 74#define CONFIG_DWC_AHSATA_PORT_ID 0 75#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 76#define CONFIG_LBA48 77#define CONFIG_LIBATA 78#endif 79 80/* SPL */ 81#ifdef CONFIG_SPL 82#include "imx6_spl.h" 83#define CONFIG_SPL_SPI_SUPPORT 84#define CONFIG_SPL_LIBCOMMON_SUPPORT 85#define CONFIG_SPL_SPI_FLASH_SUPPORT 86#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 87#define CONFIG_SPL_SPI_LOAD 88#endif 89 90#define CONFIG_FEC_MXC 91#define CONFIG_MII 92#define IMX_FEC_BASE ENET_BASE_ADDR 93#define CONFIG_FEC_XCV_TYPE MII100 94#define CONFIG_ETHPRIME "FEC" 95#define CONFIG_FEC_MXC_PHYADDR 0x5 96#define CONFIG_PHYLIB 97#define CONFIG_PHY_SMSC 98 99#ifndef CONFIG_SPL 100#define CONFIG_CMD_EEPROM 101#define CONFIG_ENV_EEPROM_IS_ON_I2C 102#define CONFIG_SYS_I2C_EEPROM_BUS 1 103#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 104#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 105#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 106#endif 107 108/* Miscellaneous commands */ 109#define CONFIG_CMD_BMODE 110 111#define CONFIG_PREBOOT "" 112 113/* Print Buffer Size */ 114#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 115 116/* Physical Memory Map */ 117#define CONFIG_NR_DRAM_BANKS 1 118#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 119 120#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 121#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 122#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 123 124#define CONFIG_SYS_INIT_SP_OFFSET \ 125 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 126#define CONFIG_SYS_INIT_SP_ADDR \ 127 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 128 129/* Environment organization */ 130#define CONFIG_ENV_IS_IN_SPI_FLASH 131#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */ 132#define CONFIG_ENV_OFFSET (1024 * 1024) 133/* M25P16 has an erase size of 64 KiB */ 134#define CONFIG_ENV_SECT_SIZE (64 * 1024) 135#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 136#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 137#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 138#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 139 140#define CONFIG_BOOTP_SERVERIP 141#define CONFIG_BOOTP_BOOTFILE 142 143#endif /* __CONFIG_H */ 144