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12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_PDM360NG 1
16#define CONFIG_DISPLAY_BOARDINFO
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32
33#define CONFIG_E300 1
34#define CONFIG_FSL_DIU_FB 1
35
36#define CONFIG_SYS_TEXT_BASE 0xF0000000
37
38
39#define CONFIG_SYS_DEVICE_NULLDEV
40#define CONFIG_SILENT_CONSOLE
41
42
43#define CONFIG_VIDEO
44
45#if defined(CONFIG_VIDEO)
46#define CONFIG_CFB_CONSOLE
47#define CONFIG_VGA_AS_SINGLE_DEVICE
48#define CONFIG_SPLASH_SCREEN
49#define CONFIG_VIDEO_LOGO
50#define CONFIG_VIDEO_BMP_RLE8
51#endif
52
53#define CONFIG_SYS_MPC512X_CLKIN 33333333
54
55#define CONFIG_MISC_INIT_R
56
57#define CONFIG_SYS_IMMR 0x80000000
58#define CONFIG_SYS_DIU_ADDR ((CONFIG_SYS_IMMR) + 0x2100)
59
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64
65#define CONFIG_SYS_DDR_BASE 0x00000000
66#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
67#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000
68
69
70#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000012
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117
118#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A40
119#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
120#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
121#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
122
123
124
125
126#define CONFIG_SYS_MDDRC_SYS_CFG_ALT1 0xE8604A40
127#define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E
128#define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168
129#define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863
130
131#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
132
133#define CONFIG_SYS_DDRCMD_NOP 0x01380000
134#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
135#define CONFIG_SYS_DDRCMD_EM2 0x01020000
136#define CONFIG_SYS_DDRCMD_EM3 0x01030000
137
138#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010040
139#define CONFIG_SYS_DDRCMD_RES_DLL 0x01000100
140#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
141#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
142
143#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x010107C0
144
145#define CONFIG_SYS_DDRCMD_OCD_EXIT 0x01010440
146
147
148#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
149#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
150#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
151#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
152#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
153#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
154#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
155#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
156#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
157#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
158#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
159#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
160#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
161#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
162#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
163#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
164#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
165#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
166#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
167#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
168#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
169#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
170#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
171
172
173
174
175#define CONFIG_SYS_FLASH_CFI
176#define CONFIG_FLASH_CFI_DRIVER
177#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
178
179#define CONFIG_SYS_FLASH_BASE 0xF0000000
180#define CONFIG_SYS_FLASH_SIZE 0x08000000
181
182#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_FLASH_BASE + \
183 CONFIG_SYS_FLASH_SIZE)
184#define CONFIG_SYS_MAX_FLASH_SECT 512
185#define CONFIG_SYS_MAX_FLASH_BANKS 2
186#define CONFIG_SYS_FLASH_BANKS_LIST \
187 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
188
189#define CONFIG_SYS_SRAM_BASE 0x50000000
190#define CONFIG_SYS_SRAM_SIZE 0x00020000
191
192#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH1_BASE
193#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
194
195
196#define CONFIG_SYS_CS0_CFG 0x05059350
197
198#define CONFIG_SYS_CS1_CFG 0x05059350
199
200#define CONFIG_SYS_MRAM_BASE 0x50040000
201#define CONFIG_SYS_MRAM_SIZE 0x00020000
202#define CONFIG_SYS_CS2_START CONFIG_SYS_MRAM_BASE
203#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_MRAM_SIZE
204
205
206#define CONFIG_SYS_CS2_CFG 0x05059110
207
208
209#define CONFIG_SYS_CS_ALETIMING 0x00000007
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211
212
213
214#define CONFIG_CMD_NAND
215#define CONFIG_NAND_MPC5121_NFC
216#define CONFIG_SYS_NAND_BASE 0x40000000
217#define CONFIG_SYS_MAX_NAND_DEVICE 1
218#define CONFIG_SYS_NAND_SELECT_DEVICE
219
220
221
222
223#define CONFIG_FSL_NFC_WIDTH 1
224#define CONFIG_FSL_NFC_WRITE_SIZE 2048
225#define CONFIG_FSL_NFC_SPARE_SIZE 64
226#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
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228
229
230
231#define CONFIG_CMD_MTDPARTS
232#define CONFIG_MTD_DEVICE
233#define CONFIG_FLASH_CFI_MTD
234#define MTDIDS_DEFAULT "nor0=f0000000.flash,nor1=f8000000.flash," \
235 "nand0=MPC5121 NAND"
236
237
238
239
240#define MTDPARTS_DEFAULT "mtdparts=f0000000.flash:512k(u-boot)," \
241 "256k(environment1)," \
242 "256k(environment2)," \
243 "256k(splash-factory)," \
244 "2m(FIT: recovery)," \
245 "4608k(fs-recovery)," \
246 "256k(splash-customer),"\
247 "5m(FIT: kernel+dtb)," \
248 "64m(rootfs squash)ro," \
249 "51m(userfs ubi);" \
250 "f8000000.flash:-(unused);" \
251 "MPC5121 NAND:1024m(extended-userfs)"
252
253
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255
256
257#ifdef CONFIG_CMD_MTDPARTS
258#define CONFIG_FDT_FIXUP_PARTITIONS
259#endif
260
261#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
262#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
263#ifdef CONFIG_FSL_DIU_FB
264#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
265#else
266#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
267#endif
268
269
270
271
272#define CONFIG_CONS_INDEX 1
273
274
275
276
277#define CONFIG_PSC_CONSOLE 6
278#if CONFIG_PSC_CONSOLE != 6
279#error CONFIG_PSC_CONSOLE must be 6
280#endif
281
282#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC6_TX_SIZE
283#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC6_TX_ADDR
284#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE
285#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR
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289
290#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
291 CLOCK_SCCR1_LPC_EN | \
292 CLOCK_SCCR1_NFC_EN | \
293 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
294 CLOCK_SCCR1_PSCFIFO_EN | \
295 CLOCK_SCCR1_DDR_EN | \
296 CLOCK_SCCR1_FEC_EN | \
297 CLOCK_SCCR1_TPR_EN)
298
299#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
300 CLOCK_SCCR2_SPDIF_EN | \
301 CLOCK_SCCR2_DIU_EN | \
302 CLOCK_SCCR2_I2C_EN)
303
304
305
306
307#define CONFIG_SYS_PSC1
308#define CONFIG_SYS_PSC4
309#define CONFIG_SYS_PSC6
310
311
312
313
314#define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY 5000
315#define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE 38400
316
317
318
319
320#define CONFIG_HARD_I2C
321#define CONFIG_I2C_MULTI_BUS
322#define CONFIG_I2C_CMD_TREE
323
324#define CONFIG_SYS_I2C_SPEED 100000
325#define CONFIG_SYS_I2C_SLAVE 0x7F
326
327
328
329
330#undef CONFIG_FSL_IIM
331
332
333
334
335#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
336#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
337#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
338#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
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340
341
342
343#define CONFIG_SYS_I2C_EEPROM_BUS_NUM 0
344#define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET 0x10
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346
347
348
349#define CONFIG_ENV_OVERWRITE
350
351
352
353
354#define CONFIG_MPC512x_FEC 1
355#define CONFIG_PHY_ADDR 0x1F
356#define CONFIG_MII 1
357#define CONFIG_FEC_AN_TIMEOUT 1
358#define CONFIG_HAS_ETH0
359
360
361
362
363#define CONFIG_RTC_M41T62
364#define CONFIG_SYS_I2C_RTC_ADDR 0x68
365
366
367
368
369#define CONFIG_ENV_IS_IN_FLASH 1
370
371#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
372 CONFIG_SYS_MONITOR_LEN)
373#define CONFIG_ENV_SIZE 0x2000
374#define CONFIG_ENV_SECT_SIZE 0x40000
375
376
377#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
378#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
379
380#define CONFIG_LOADS_ECHO 1
381#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
382
383#define CONFIG_CMD_DATE
384#define CONFIG_CMD_EEPROM
385#define CONFIG_CMD_REGINFO
386
387#undef CONFIG_CMD_FUSE
388
389#ifdef CONFIG_VIDEO
390#define CONFIG_CMD_BMP
391#endif
392
393
394
395
396#define CONFIG_SYS_LONGHELP
397#define CONFIG_SYS_LOAD_ADDR 0x2000000
398
399#ifdef CONFIG_CMD_KGDB
400 #define CONFIG_SYS_CBSIZE 1024
401#else
402 #define CONFIG_SYS_CBSIZE 256
403#endif
404
405
406#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
407
408#define CONFIG_SYS_MAXARGS 16
409
410#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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417
418
419#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
420
421
422#define CONFIG_SYS_DCACHE_SIZE 32768
423#define CONFIG_SYS_CACHELINE_SIZE 32
424#ifdef CONFIG_CMD_KGDB
425
426#define CONFIG_SYS_CACHELINE_SHIFT 5
427#endif
428
429#define CONFIG_SYS_HID0_INIT 0x000000000
430#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
431#define CONFIG_SYS_HID2 HID2_HBE
432
433#define CONFIG_HIGH_BATS 1
434
435#ifdef CONFIG_CMD_KGDB
436#define CONFIG_KGDB_BAUDRATE 230400
437#endif
438
439
440#define CONFIG_POST (CONFIG_SYS_POST_COPROC)
441
442
443
444
445#define CONFIG_TIMESTAMP
446
447#define CONFIG_HOSTNAME pdm360ng
448
449#define CONFIG_LOADADDR 400000
450
451
452#define CONFIG_PREBOOT "echo;" \
453 "echo PDM360NG SAMPLE;" \
454 "echo"
455
456#define CONFIG_BOOTCOMMAND "run env_cont"
457
458#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
459
460#define OF_CPU "PowerPC,5121@0"
461#define OF_SOC_COMPAT "fsl,mpc5121-immr"
462#define OF_TBCLK (bd->bi_busfreq / 4)
463#define OF_STDOUT_PATH "/soc@80000000/serial@11600"
464
465
466
467
468#include "mpc5121-common.h"
469
470#endif
471