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15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18
19
20
21
22#ifndef CONFIG_RAINIER
23#define CONFIG_440EPX 1
24#define CONFIG_HOSTNAME sequoia
25#else
26#define CONFIG_440GRX 1
27#define CONFIG_HOSTNAME rainier
28#endif
29#define CONFIG_440 1
30
31#ifndef CONFIG_SYS_TEXT_BASE
32#define CONFIG_SYS_TEXT_BASE 0xFFF80000
33#endif
34
35
36
37
38#include "amcc-common.h"
39
40
41#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
42 33333333 : 33000000)
43
44
45
46
47
48#undef CONFIG_VIDEO
49
50#ifdef CONFIG_VIDEO
51
52
53
54
55#define CONFIG_4xx_DCACHE
56#endif
57
58#define CONFIG_BOARD_EARLY_INIT_F 1
59#define CONFIG_MISC_INIT_R 1
60
61
62
63
64
65#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
66#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
67#define CONFIG_SYS_FLASH_BASE 0xfc000000
68#define CONFIG_SYS_NAND_ADDR 0xd0000000
69#define CONFIG_SYS_OCM_BASE 0xe0010000
70#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
71#define CONFIG_SYS_PCI_BASE 0xe0000000
72#define CONFIG_SYS_PCI_MEMBASE 0x80000000
73#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
74#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
75#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
76
77#define CONFIG_SYS_USB2D0_BASE 0xe0000100
78#define CONFIG_SYS_USB_DEVICE 0xe0000000
79#define CONFIG_SYS_USB_HOST 0xe0000400
80#define CONFIG_SYS_BCSR_BASE 0xc0000000
81
82
83
84
85
86#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
87#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
88#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
89#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
90
91
92
93
94#define CONFIG_CONS_INDEX 1
95#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200
96
97
98
99
100#if defined(CONFIG_SYS_RAMBOOT)
101#define CONFIG_ENV_IS_NOWHERE
102#define CONFIG_ENV_SIZE (8 << 10)
103#else
104#define CONFIG_ENV_IS_IN_FLASH
105#endif
106
107#if defined(CONFIG_CMD_FLASH)
108
109
110
111#define CONFIG_SYS_FLASH_CFI
112#define CONFIG_FLASH_CFI_DRIVER
113
114#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
115
116#define CONFIG_SYS_MAX_FLASH_BANKS 1
117#define CONFIG_SYS_MAX_FLASH_SECT 512
118
119#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
120#define CONFIG_SYS_FLASH_WRITE_TOUT 500
121
122#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
123#define CONFIG_SYS_FLASH_PROTECTION 1
124
125#define CONFIG_SYS_FLASH_EMPTY_INFO
126#define CONFIG_SYS_FLASH_QUIET_TEST 1
127#endif
128
129#ifdef CONFIG_ENV_IS_IN_FLASH
130#define CONFIG_ENV_SECT_SIZE 0x20000
131#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
132#define CONFIG_ENV_SIZE 0x2000
133
134
135#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
136#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
137#endif
138
139
140
141
142#define CONFIG_SYS_MBYTES_SDRAM (256)
143#if !defined(CONFIG_SYS_RAMBOOT)
144#define CONFIG_DDR_DATA_EYE
145#endif
146#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
147
148
149
150
151
152#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
153
154#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
155#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
156#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
157#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
158
159
160#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
161#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
162#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
163
164
165#define CONFIG_DTT_LM75 1
166#define CONFIG_DTT_AD7414 1
167#define CONFIG_DTT_SENSORS {0}
168#define CONFIG_SYS_DTT_MAX_TEMP 70
169#define CONFIG_SYS_DTT_LOW_TEMP -30
170#define CONFIG_SYS_DTT_HYSTERESIS 3
171
172
173
174
175#define CONFIG_EXTRA_ENV_SETTINGS \
176 CONFIG_AMCC_DEF_ENV \
177 CONFIG_AMCC_DEF_ENV_POWERPC \
178 CONFIG_AMCC_DEF_ENV_PPC_OLD \
179 CONFIG_AMCC_DEF_ENV_NOR_UPD \
180 "kernel_addr=FC000000\0" \
181 "ramdisk_addr=FC180000\0" \
182 ""
183
184#define CONFIG_M88E1111_PHY 1
185#define CONFIG_IBM_EMAC4_V4 1
186#define CONFIG_PHY_ADDR 0
187
188#define CONFIG_PHY_RESET 1
189#define CONFIG_PHY_GIGE 1
190
191#define CONFIG_HAS_ETH0
192#define CONFIG_HAS_ETH1 1
193#define CONFIG_PHY1_ADDR 1
194
195
196#ifdef CONFIG_440EPX
197
198#undef CONFIG_USB_EHCI
199
200#ifdef CONFIG_USB_EHCI
201#define CONFIG_USB_EHCI_PPC4XX
202#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
203#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
204#define CONFIG_EHCI_MMIO_BIG_ENDIAN
205#define CONFIG_EHCI_DESC_BIG_ENDIAN
206#else
207#define CONFIG_USB_OHCI_NEW
208#define CONFIG_SYS_OHCI_BE_CONTROLLER
209
210#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
211#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
212#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
213#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
214#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
215#endif
216
217
218#define USB_2_0_DEVICE
219
220#endif
221
222
223#define CONFIG_MAC_PARTITION
224#define CONFIG_DOS_PARTITION
225#define CONFIG_ISO_PARTITION
226
227
228
229
230#define CONFIG_CMD_CHIP_CONFIG
231#define CONFIG_CMD_DTT
232#define CONFIG_CMD_NAND
233#define CONFIG_CMD_PCI
234#define CONFIG_CMD_SDRAM
235
236#ifdef CONFIG_440EPX
237#endif
238
239#ifndef CONFIG_RAINIER
240#define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
241#else
242#define CONFIG_SYS_POST_FPU_ON 0
243#endif
244
245
246
247
248
249
250#if defined(CONFIG_SYS_RAMBOOT)
251#define CONFIG_SYS_POST_MEMORY_ON 0
252#else
253#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
254#endif
255
256
257#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
258 CONFIG_SYS_POST_CPU | \
259 CONFIG_SYS_POST_ETHER | \
260 CONFIG_SYS_POST_FPU_ON | \
261 CONFIG_SYS_POST_I2C | \
262 CONFIG_SYS_POST_MEMORY_ON | \
263 CONFIG_SYS_POST_SPR | \
264 CONFIG_SYS_POST_UART)
265
266#define CONFIG_LOGBUFFER
267#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000
268
269#define CONFIG_SYS_CONSOLE_IS_IN_ENV
270
271#define CONFIG_SUPPORT_VFAT
272
273
274
275
276
277#define CONFIG_PCI
278#define CONFIG_PCI_INDIRECT_BRIDGE
279#define CONFIG_PCI_PNP
280#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0
281#define CONFIG_PCI_SCAN_SHOW
282#define CONFIG_SYS_PCI_TARGBASE 0x80000000
283
284
285#define CONFIG_SYS_PCI_TARGET_INIT
286#define CONFIG_SYS_PCI_MASTER_INIT
287#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
288
289#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8
290#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe
291
292
293
294
295
296
297
298
299#if !defined(CONFIG_SYS_RAMBOOT)
300#define CONFIG_SYS_NAND_CS 3
301
302#define CONFIG_SYS_EBC_PB0AP 0x03017200
303#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
304
305
306#define CONFIG_SYS_EBC_PB3AP 0x018003c0
307#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
308#else
309#define CONFIG_SYS_NAND_CS 0
310
311#define CONFIG_SYS_EBC_PB3AP 0x03017200
312#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000)
313
314
315#define CONFIG_SYS_EBC_PB0AP 0x018003c0
316#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
317#endif
318
319
320#define CONFIG_SYS_EBC_PB2AP 0x24814580
321#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000)
322
323#define CONFIG_SYS_BCSR5_PCI66EN 0x80
324
325
326
327
328#define CONFIG_SYS_MAX_NAND_DEVICE 1
329#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
330#define CONFIG_SYS_NAND_SELECT_DEVICE 1
331
332
333
334
335
336#define CONFIG_SYS_4xx_GPIO_TABLE { \
337{ \
338 \
339{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
340{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
341{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
342{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
343{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
344{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
345{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
346{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
347{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
348{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
349{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
350{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
351{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
352{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
353{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
354{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
355{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
356{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
357{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
358{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
359{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
360{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
361{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
362{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
363{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
364{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
365{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
366{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
367{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
368{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
369{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
370{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
371}, \
372{ \
373 \
374{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
375{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
376{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
377{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
378{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
379{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
380{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
381{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
382{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
383{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
384{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
385{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
386{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
387{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
388{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
389{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
390{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
391{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
392{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
393{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
394{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
395{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
396{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
397{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
398{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
399{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
400{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
401{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
402{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
403{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
404{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
405{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
406} \
407}
408
409#ifdef CONFIG_VIDEO
410#define CONFIG_BIOSEMU
411#define CONFIG_ATI_RADEON_FB
412#define VIDEO_IO_OFFSET 0xe8000000
413#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
414#define CONFIG_VIDEO_SW_CURSOR
415#define CONFIG_VIDEO_LOGO
416#define CONFIG_CFB_CONSOLE
417#define CONFIG_SPLASH_SCREEN
418#define CONFIG_VGA_AS_SINGLE_DEVICE
419#define CONFIG_CMD_BMP
420#endif
421
422#endif
423