LXR uboot/include/configs/sequoia.h

   1/*
   2 * (C) Copyright 2006-2008
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * (C) Copyright 2006
   6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7 * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8 *
   9 * SPDX-License-Identifier:     GPL-2.0+
  10 */
  11
  12/*
  13 * sequoia.h - configuration for Sequoia & Rainier boards
  14 */
  15#ifndef __CONFIG_H
  16#define __CONFIG_H
  17
  18/*
  19 * High Level Configuration Options
  20 */
  21/* This config file is used for Sequoia (440EPx) and Rainier (440GRx)   */
  22#ifndef CONFIG_RAINIER
  23#define CONFIG_440EPX           1       /* Specific PPC440EPx           */
  24#define CONFIG_HOSTNAME         sequoia
  25#else
  26#define CONFIG_440GRX           1       /* Specific PPC440GRx           */
  27#define CONFIG_HOSTNAME         rainier
  28#endif
  29#define CONFIG_440              1       /* ... PPC440 family            */
  30
  31#ifndef CONFIG_SYS_TEXT_BASE
  32#define CONFIG_SYS_TEXT_BASE    0xFFF80000
  33#endif
  34
  35/*
  36 * Include common defines/options for all AMCC eval boards
  37 */
  38#include "amcc-common.h"
  39
  40/* Detect Sequoia PLL input clock automatically via CPLD bit            */
  41#define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
  42                                33333333 : 33000000)
  43
  44/*
  45 * Define this if you want support for video console with radeon 9200 pci card
  46 * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
  47 */
  48#undef CONFIG_VIDEO
  49
  50#ifdef CONFIG_VIDEO
  51/*
  52 * 44x dcache supported is working now on sequoia, but we don't enable
  53 * it yet since it needs further testing
  54 */
  55#define CONFIG_4xx_DCACHE               /* enable dcache                */
  56#endif
  57
  58#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  59#define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  60
  61/*
  62 * Base addresses -- Note these are effective addresses where the actual
  63 * resources get mapped (not physical addresses).
  64 */
  65#define CONFIG_SYS_TLB_FOR_BOOT_FLASH   0x0003
  66#define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  67#define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  68#define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  69#define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  70#define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  71#define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  72#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  73#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  74#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  75#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  76
  77#define CONFIG_SYS_USB2D0_BASE          0xe0000100
  78#define CONFIG_SYS_USB_DEVICE           0xe0000000
  79#define CONFIG_SYS_USB_HOST             0xe0000400
  80#define CONFIG_SYS_BCSR_BASE            0xc0000000
  81
  82/*
  83 * Initial RAM & stack pointer
  84 */
  85/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  86#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  87#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  88#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  89#define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  90
  91/*
  92 * Serial Port
  93 */
  94#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  95#define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
  96
  97/*
  98 * Environment
  99 */
 100#if defined(CONFIG_SYS_RAMBOOT)
 101#define CONFIG_ENV_IS_NOWHERE           /* Store env in memory only     */
 102#define CONFIG_ENV_SIZE         (8 << 10)
 103#else
 104#define CONFIG_ENV_IS_IN_FLASH          /* use FLASH for environ vars   */
 105#endif
 106
 107#if defined(CONFIG_CMD_FLASH)
 108/*
 109 * FLASH related
 110 */
 111#define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 112#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 113
 114#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 115
 116#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks         */
 117#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip  */
 118
 119#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)    */
 120#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)    */
 121
 122#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)   */
 123#define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection      */
 124
 125#define CONFIG_SYS_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 126#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash      */
 127#endif /* CONFIG_CMD_FLASH */
 128
 129#ifdef CONFIG_ENV_IS_IN_FLASH
 130#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector        */
 131#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 132#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector   */
 133
 134/* Address and size of Redundant Environment Sector     */
 135#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 136#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 137#endif
 138
 139/*
 140 * DDR SDRAM
 141 */
 142#define CONFIG_SYS_MBYTES_SDRAM        (256)    /* 256MB                        */
 143#if !defined(CONFIG_SYS_RAMBOOT)
 144#define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 145#endif
 146#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes     */
 147                                        /* 440EPx errata CHIP 11        */
 148
 149/*
 150 * I2C
 151 */
 152#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 153
 154#define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 155#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 156#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 157#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 158
 159/* I2C bootstrap EEPROM */
 160#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 161#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 162#define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 163
 164/* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 165#define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 166#define CONFIG_DTT_AD7414       1       /* use AD7414                   */
 167#define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 168#define CONFIG_SYS_DTT_MAX_TEMP 70
 169#define CONFIG_SYS_DTT_LOW_TEMP -30
 170#define CONFIG_SYS_DTT_HYSTERESIS       3
 171
 172/*
 173 * Default environment variables
 174 */
 175#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 176        CONFIG_AMCC_DEF_ENV                                             \
 177        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 178        CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 179        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 180        "kernel_addr=FC000000\0"                                        \
 181        "ramdisk_addr=FC180000\0"                                       \
 182        ""
 183
 184#define CONFIG_M88E1111_PHY     1
 185#define CONFIG_IBM_EMAC4_V4     1
 186#define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 187
 188#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 189#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 190
 191#define CONFIG_HAS_ETH0
 192#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 193#define CONFIG_PHY1_ADDR        1
 194
 195/* USB */
 196#ifdef CONFIG_440EPX
 197
 198#undef CONFIG_USB_EHCI  /* OHCI by default */
 199
 200#ifdef CONFIG_USB_EHCI
 201#define CONFIG_USB_EHCI_PPC4XX
 202#define CONFIG_SYS_PPC4XX_USB_ADDR      0xe0000300
 203#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 204#define CONFIG_EHCI_MMIO_BIG_ENDIAN
 205#define CONFIG_EHCI_DESC_BIG_ENDIAN
 206#else /* CONFIG_USB_EHCI */
 207#define CONFIG_USB_OHCI_NEW
 208#define CONFIG_SYS_OHCI_BE_CONTROLLER
 209
 210#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
 211#define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 212#define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 213#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 214#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 215#endif
 216
 217/* Comment this out to enable USB 1.1 device */
 218#define USB_2_0_DEVICE
 219
 220#endif /* CONFIG_440EPX */
 221
 222/* Partitions */
 223#define CONFIG_MAC_PARTITION
 224#define CONFIG_DOS_PARTITION
 225#define CONFIG_ISO_PARTITION
 226
 227/*
 228 * Commands additional to the ones defined in amcc-common.h
 229 */
 230#define CONFIG_CMD_CHIP_CONFIG
 231#define CONFIG_CMD_DTT
 232#define CONFIG_CMD_NAND
 233#define CONFIG_CMD_PCI
 234#define CONFIG_CMD_SDRAM
 235
 236#ifdef CONFIG_440EPX
 237#endif
 238
 239#ifndef CONFIG_RAINIER
 240#define CONFIG_SYS_POST_FPU_ON          CONFIG_SYS_POST_FPU
 241#else
 242#define CONFIG_SYS_POST_FPU_ON          0
 243#endif
 244
 245/*
 246 * Don't run the memory POST on the NAND-booting version. It will
 247 * overwrite part of the U-Boot image which is already loaded from NAND
 248 * to SDRAM.
 249 */
 250#if defined(CONFIG_SYS_RAMBOOT)
 251#define CONFIG_SYS_POST_MEMORY_ON       0
 252#else
 253#define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 254#endif
 255
 256/* POST support */
 257#define CONFIG_POST             (CONFIG_SYS_POST_CACHE     | \
 258                                 CONFIG_SYS_POST_CPU       | \
 259                                 CONFIG_SYS_POST_ETHER     | \
 260                                 CONFIG_SYS_POST_FPU_ON    | \
 261                                 CONFIG_SYS_POST_I2C       | \
 262                                 CONFIG_SYS_POST_MEMORY_ON | \
 263                                 CONFIG_SYS_POST_SPR       | \
 264                                 CONFIG_SYS_POST_UART)
 265
 266#define CONFIG_LOGBUFFER
 267#define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 268
 269#define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* Otherwise it catches logbuffer as output */
 270
 271#define CONFIG_SUPPORT_VFAT
 272
 273/*
 274 * PCI stuff
 275 */
 276/* General PCI */
 277#define CONFIG_PCI                      /* include pci support          */
 278#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 279#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 280#define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 281#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 282#define CONFIG_SYS_PCI_TARGBASE 0x80000000      /* PCIaddr mapped to    */
 283                                                /*   CONFIG_SYS_PCI_MEMBASE     */
 284/* Board-specific PCI */
 285#define CONFIG_SYS_PCI_TARGET_INIT
 286#define CONFIG_SYS_PCI_MASTER_INIT
 287#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 288
 289#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC                         */
 290#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever                     */
 291
 292/*
 293 * External Bus Controller (EBC) Setup
 294 */
 295
 296/*
 297 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 298 */
 299#if !defined(CONFIG_SYS_RAMBOOT)
 300#define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx   */
 301/* Memory Bank 0 (NOR-FLASH) initialization                             */
 302#define CONFIG_SYS_EBC_PB0AP            0x03017200
 303#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 304
 305/* Memory Bank 3 (NAND-FLASH) initialization                            */
 306#define CONFIG_SYS_EBC_PB3AP            0x018003c0
 307#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 308#else
 309#define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx   */
 310/* Memory Bank 3 (NOR-FLASH) initialization                             */
 311#define CONFIG_SYS_EBC_PB3AP            0x03017200
 312#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 313
 314/* Memory Bank 0 (NAND-FLASH) initialization                            */
 315#define CONFIG_SYS_EBC_PB0AP            0x018003c0
 316#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 317#endif
 318
 319/* Memory Bank 2 (CPLD) initialization                                  */
 320#define CONFIG_SYS_EBC_PB2AP            0x24814580
 321#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x38000)
 322
 323#define CONFIG_SYS_BCSR5_PCI66EN        0x80
 324
 325/*
 326 * NAND FLASH
 327 */
 328#define CONFIG_SYS_MAX_NAND_DEVICE      1
 329#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 330#define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips */
 331
 332/*
 333 * PPC440 GPIO Configuration
 334 */
 335/* test-only: take GPIO init from pcs440ep ???? in config file */
 336#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 337{                                                                                       \
 338/* GPIO Core 0 */                                                                       \
 339{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 340{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 341{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 342{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 343{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 344{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 345{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 346{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 347{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 348{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 349{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 350{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 351{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 352{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 353{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14                                */      \
 354{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15                                */      \
 355{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)                      */      \
 356{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)                      */      \
 357{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)                      */      \
 358{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)                      */      \
 359{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 360{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 361{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 362{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 363{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)                      */      \
 364{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)                      */      \
 365{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 366{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 367{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28                USB2D_TXVALID   */      \
 368{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 369{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 370{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 371},                                                                                      \
 372{                                                                                       \
 373/* GPIO Core 1 */                                                                       \
 374{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 375{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 376{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
 377{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 378{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N    EBC_DATA(0)     UART3_SIN*/ \
 379{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 380{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT    */      \
 381{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN      */      \
 382{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 383{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 384{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 385{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 386{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 387{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 388{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 389{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 390{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 391{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 392{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 393{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 394{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 395{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 396{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 397{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 398{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 399{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 400{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 401{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 402{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 403{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 404{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 405{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 406}                                                                                       \
 407}
 408
 409#ifdef CONFIG_VIDEO
 410#define CONFIG_BIOSEMU                  /* x86 bios emulator for vga bios */
 411#define CONFIG_ATI_RADEON_FB            /* use radeon framebuffer driver */
 412#define VIDEO_IO_OFFSET                 0xe8000000
 413#define CONFIG_SYS_ISA_IO_BASE_ADDRESS          VIDEO_IO_OFFSET
 414#define CONFIG_VIDEO_SW_CURSOR
 415#define CONFIG_VIDEO_LOGO
 416#define CONFIG_CFB_CONSOLE
 417#define CONFIG_SPLASH_SCREEN
 418#define CONFIG_VGA_AS_SINGLE_DEVICE
 419#define CONFIG_CMD_BMP
 420#endif
 421
 422#endif /* __CONFIG_H */
 423