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12#ifndef __VEXPRESS_COMMON_H
13#define __VEXPRESS_COMMON_H
14
15
16
17
18
19#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
20
21#define V2M_PA_CS0 0x40000000
22#define V2M_PA_CS1 0x44000000
23#define V2M_PA_CS2 0x48000000
24#define V2M_PA_CS3 0x4c000000
25#define V2M_PA_CS7 0x10000000
26
27#define V2M_PERIPH_OFFSET(x) (x << 12)
28#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
29#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
30#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
31
32#define V2M_BASE 0x60000000
33#define CONFIG_SYS_TEXT_BASE 0x60800000
34#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
35
36#define V2M_PA_CS0 0x08000000
37#define V2M_PA_CS1 0x0c000000
38#define V2M_PA_CS2 0x14000000
39#define V2M_PA_CS3 0x18000000
40#define V2M_PA_CS7 0x1c000000
41
42#define V2M_PERIPH_OFFSET(x) (x << 16)
43#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
44#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
45#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
46
47#define V2M_BASE 0x80000000
48#define CONFIG_SYS_TEXT_BASE 0x80800000
49#endif
50
51
52
53
54#define V2M_NOR0 (V2M_PA_CS0)
55#define V2M_NOR1 (V2M_PA_CS1)
56#define V2M_SRAM (V2M_PA_CS2)
57#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
58#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000)
59#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
60
61
62#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
63#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
64#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
65#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
66
67#define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
68#define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
69#define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
70#define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
71
72#define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
73
74#define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
75#define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
76
77#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
78#define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
79
80#define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
81
82#define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
83#define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32)
84
85
86#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
87#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
88#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
89
90
91
92
93#define SYS_CFG_START (1 << 31)
94#define SYS_CFG_WRITE (1 << 30)
95#define SYS_CFG_OSC (1 << 20)
96#define SYS_CFG_VOLT (2 << 20)
97#define SYS_CFG_AMP (3 << 20)
98#define SYS_CFG_TEMP (4 << 20)
99#define SYS_CFG_RESET (5 << 20)
100#define SYS_CFG_SCC (6 << 20)
101#define SYS_CFG_MUXFPGA (7 << 20)
102#define SYS_CFG_SHUTDOWN (8 << 20)
103#define SYS_CFG_REBOOT (9 << 20)
104#define SYS_CFG_DVIMODE (11 << 20)
105#define SYS_CFG_POWER (12 << 20)
106#define SYS_CFG_SITE_MB (0 << 16)
107#define SYS_CFG_SITE_DB1 (1 << 16)
108#define SYS_CFG_SITE_DB2 (2 << 16)
109#define SYS_CFG_STACK(n) ((n) << 12)
110
111#define SYS_CFG_ERR (1 << 1)
112#define SYS_CFG_COMPLETE (1 << 0)
113
114
115#define SYS_ID V2M_SYSREGS
116#define CONFIG_REVISION_TAG 1
117
118#define CONFIG_SYS_MEMTEST_START V2M_BASE
119#define CONFIG_SYS_MEMTEST_END 0x20000000
120
121#define CONFIG_CMDLINE_TAG 1
122#define CONFIG_SETUP_MEMORY_TAGS 1
123#define CONFIG_SYS_L2CACHE_OFF 1
124#define CONFIG_INITRD_TAG 1
125
126
127#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
128
129#define SCTL_BASE V2M_SYSCTL
130#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
131
132#define CONFIG_SYS_TIMER_RATE 1000000
133#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
134#define CONFIG_SYS_TIMER_COUNTS_DOWN
135
136
137#define CONFIG_SMC911X 1
138#define CONFIG_SMC911X_32_BIT 1
139#define CONFIG_SMC911X_BASE V2M_LAN9118
140
141
142#define CONFIG_PL011_SERIAL
143#define CONFIG_PL011_CLOCK 24000000
144#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
145 (void *)CONFIG_SYS_SERIAL1}
146#define CONFIG_CONS_INDEX 0
147
148#define CONFIG_BAUDRATE 38400
149#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
150#define CONFIG_SYS_SERIAL0 V2M_UART0
151#define CONFIG_SYS_SERIAL1 V2M_UART1
152
153#define CONFIG_MMC 1
154#define CONFIG_GENERIC_MMC
155#define CONFIG_ARM_PL180_MMCI
156#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI
157#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
158#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
159
160
161#define CONFIG_BOOTP_BOOTFILESIZE
162#define CONFIG_BOOTP_BOOTPATH
163#define CONFIG_BOOTP_GATEWAY
164#define CONFIG_BOOTP_HOSTNAME
165
166
167#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000)
168#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
169
170
171#define CONFIG_NR_DRAM_BANKS 2
172#define PHYS_SDRAM_1 (V2M_BASE)
173#define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + \
174 ((unsigned int)0x20000000))
175#define PHYS_SDRAM_1_SIZE 0x20000000
176#define PHYS_SDRAM_2_SIZE 0x20000000
177
178
179#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
180#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
181#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
182 CONFIG_SYS_INIT_RAM_SIZE - \
183 GENERATED_GBL_DATA_SIZE)
184#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
185
186#include <config_distro_defaults.h>
187
188
189#define CONFIG_BOOTCOMMAND \
190 "run distro_bootcmd; " \
191 "run bootflash; "
192
193#define BOOT_TARGET_DEVICES(func) \
194 func(MMC, mmc, 1) \
195 func(MMC, mmc, 0) \
196 func(PXE, pxe, na) \
197 func(DHCP, dhcp, na)
198#include <config_distro_bootcmd.h>
199
200#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
201#define CONFIG_PLATFORM_ENV_SETTINGS \
202 "loadaddr=0x80008000\0" \
203 "ramdisk_addr_r=0x61000000\0" \
204 "kernel_addr=0x44100000\0" \
205 "ramdisk_addr=0x44800000\0" \
206 "maxramdisk=0x1800000\0" \
207 "pxefile_addr_r=0x88000000\0" \
208 "scriptaddr=0x88000000\0" \
209 "kernel_addr_r=0x80008000\0"
210#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
211#define CONFIG_PLATFORM_ENV_SETTINGS \
212 "loadaddr=0xa0008000\0" \
213 "ramdisk_addr_r=0x81000000\0" \
214 "kernel_addr=0x0c100000\0" \
215 "ramdisk_addr=0x0c800000\0" \
216 "maxramdisk=0x1800000\0" \
217 "pxefile_addr_r=0xa8000000\0" \
218 "scriptaddr=0xa8000000\0" \
219 "kernel_addr_r=0xa0008000\0"
220#endif
221#define CONFIG_EXTRA_ENV_SETTINGS \
222 CONFIG_PLATFORM_ENV_SETTINGS \
223 BOOTENV \
224 "console=ttyAMA0,38400n8\0" \
225 "dram=1024M\0" \
226 "root=/dev/sda1 rw\0" \
227 "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
228 "24M@0x2000000(initrd)\0" \
229 "flashargs=setenv bootargs root=${root} console=${console} " \
230 "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
231 "devtmpfs.mount=0 vmalloc=256M\0" \
232 "bootflash=run flashargs; " \
233 "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
234 "bootm ${kernel_addr} ${ramdisk_addr_r}\0"
235
236
237#define PHYS_FLASH_SIZE 0x04000000
238#define CONFIG_SYS_FLASH_CFI 1
239#define CONFIG_FLASH_CFI_DRIVER 1
240#define CONFIG_SYS_FLASH_SIZE 0x04000000
241#define CONFIG_SYS_MAX_FLASH_BANKS 2
242#define CONFIG_SYS_FLASH_BASE0 V2M_NOR0
243#define CONFIG_SYS_FLASH_BASE1 V2M_NOR1
244#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0
245
246
247#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ)
248#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ)
249
250
251#define CONFIG_SYS_MAX_FLASH_SECT 259
252#define FLASH_MAX_SECTOR_SIZE 0x00040000
253
254
255#define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE
256
257#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
258
259
260
261
262
263
264#define CONFIG_ENV_SECT_SIZE FLASH_MAX_SECTOR_SIZE
265#define CONFIG_ENV_OVERWRITE 1
266
267
268#define CONFIG_ENV_IS_IN_FLASH 1
269#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - \
270 (2 * CONFIG_ENV_SECT_SIZE))
271#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE1 + \
272 CONFIG_ENV_OFFSET)
273#define CONFIG_SYS_FLASH_PROTECTION
274#define CONFIG_SYS_FLASH_EMPTY_INFO
275#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \
276 CONFIG_SYS_FLASH_BASE1 }
277
278
279#define CONFIG_SYS_CBSIZE 512
280#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
281 sizeof(CONFIG_SYS_PROMPT) + 16)
282
283#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
284#define CONFIG_SYS_LONGHELP
285#define CONFIG_SYS_MAXARGS 16
286
287#endif
288