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18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21#define CONFIG_DISPLAY_BOARDINFO
22
23
24
25
26#ifdef CONFIG_CADDY2
27#define VME_CADDY2
28#endif
29
30
31
32
33#define CONFIG_E300 1
34#define CONFIG_MPC834x 1
35#define CONFIG_MPC8349 1
36#define CONFIG_VME8349 1
37
38#define CONFIG_SYS_TEXT_BASE 0xFFF00000
39
40#define CONFIG_MISC_INIT_R
41
42#define CONFIG_PCI
43
44#undef CONFIG_MPC83XX_PCI2
45
46#define CONFIG_PCI_66M
47#ifdef CONFIG_PCI_66M
48#define CONFIG_83XX_CLKIN 66000000
49#else
50#define CONFIG_83XX_CLKIN 33000000
51#endif
52
53#ifndef CONFIG_SYS_CLK_FREQ
54#ifdef CONFIG_PCI_66M
55#define CONFIG_SYS_CLK_FREQ 66000000
56#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
57#else
58#define CONFIG_SYS_CLK_FREQ 33000000
59#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
60#endif
61#endif
62
63#define CONFIG_SYS_IMMR 0xE0000000
64
65#undef CONFIG_SYS_DRAM_TEST
66#define CONFIG_SYS_MEMTEST_START 0x00000000
67#define CONFIG_SYS_MEMTEST_END 0x00100000
68
69
70
71
72#define CONFIG_DDR_ECC
73#define CONFIG_DDR_ECC_CMD
74#define CONFIG_SPD_EEPROM
75#define SPD_EEPROM_ADDRESS 0x54
76#define CONFIG_SYS_READ_SPD vme8349_read_spd
77#define CONFIG_SYS_83XX_DDR_USES_CS0
78
79
80
81
82
83
84
85
86
87
88
89#undef CONFIG_DDR_32BIT
90
91#define CONFIG_SYS_DDR_BASE 0x00000000
92#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
93#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
94#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
95 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
96#define CONFIG_DDR_2T_TIMING
97#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
98 | DDRCDR_ODT \
99 | DDRCDR_Q_DRN)
100
101
102
103
104
105#define CONFIG_SYS_FLASH_CFI
106#define CONFIG_FLASH_CFI_DRIVER
107#ifdef VME_CADDY2
108#define CONFIG_SYS_FLASH_BASE 0xffc00000
109#define CONFIG_SYS_FLASH_SIZE 4
110#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
111 BR_PS_16 | \
112 BR_MS_GPCM | \
113 BR_V)
114
115#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
116 | OR_GPCM_XAM \
117 | OR_GPCM_CSNT \
118 | OR_GPCM_ACS_DIV2 \
119 | OR_GPCM_XACS \
120 | OR_GPCM_SCY_15 \
121 | OR_GPCM_TRLX_SET \
122 | OR_GPCM_EHTR_SET \
123 | OR_GPCM_EAD)
124
125#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
126#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
127#else
128#define CONFIG_SYS_FLASH_BASE 0xf8000000
129#define CONFIG_SYS_FLASH_SIZE 128
130#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
131 BR_PS_16 | \
132 BR_MS_GPCM | \
133 BR_V)
134
135#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
136 | OR_GPCM_XAM \
137 | OR_GPCM_CSNT \
138 | OR_GPCM_ACS_DIV2 \
139 | OR_GPCM_XACS \
140 | OR_GPCM_SCY_15 \
141 | OR_GPCM_TRLX_SET \
142 | OR_GPCM_EHTR_SET \
143 | OR_GPCM_EAD)
144
145#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
146#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
147#endif
148
149
150#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
151#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
152 | BR_PS_32 \
153 | BR_MS_GPCM \
154 | BR_V)
155
156#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
157 | OR_GPCM_SETA)
158
159#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
160#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
161
162#define CONFIG_SYS_MAX_FLASH_BANKS 1
163#define CONFIG_SYS_MAX_FLASH_SECT 1024
164
165#undef CONFIG_SYS_FLASH_CHECKSUM
166#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
167#define CONFIG_SYS_FLASH_WRITE_TOUT 500
168
169#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
170
171#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
172#define CONFIG_SYS_RAMBOOT
173#else
174#undef CONFIG_SYS_RAMBOOT
175#endif
176
177#define CONFIG_SYS_INIT_RAM_LOCK 1
178#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000
179#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
180
181#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
182 GENERATED_GBL_DATA_SIZE)
183#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
184
185#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
186#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
187
188
189
190
191
192
193
194#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
195#define CONFIG_SYS_LBC_LBCR 0x00000000
196
197#undef CONFIG_SYS_LB_SDRAM
198
199
200
201
202#define CONFIG_CONS_INDEX 1
203#define CONFIG_SYS_NS16550_SERIAL
204#define CONFIG_SYS_NS16550_REG_SIZE 1
205#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
206
207#define CONFIG_SYS_BAUDRATE_TABLE \
208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
209
210#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
211#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
212
213#define CONFIG_CMDLINE_EDITING
214#define CONFIG_AUTO_COMPLETE
215
216
217#define CONFIG_SYS_I2C
218#define CONFIG_SYS_I2C_FSL
219#define CONFIG_SYS_FSL_I2C_SPEED 400000
220#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
221#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
222#define CONFIG_SYS_FSL_I2C2_SPEED 400000
223#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
224#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
225#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
226
227
228#define CONFIG_SYS_I2C_8574_ADDR2 0x20
229
230
231#define CONFIG_SYS_TSEC1_OFFSET 0x24000
232#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
233#define CONFIG_SYS_TSEC2_OFFSET 0x25000
234#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
235
236
237
238
239
240#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
241#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
242#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
243#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
244#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
245#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
246#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
247#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
248#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
249
250#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
251#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
252#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
253#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
254#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
255#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
256#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
257#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
258#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
259
260#if defined(CONFIG_PCI)
261
262#define PCI_64BIT
263#define PCI_ONE_PCI1
264#if defined(PCI_64BIT)
265#undef PCI_ALL_PCI1
266#undef PCI_TWO_PCI1
267#undef PCI_ONE_PCI1
268#endif
269
270#ifndef VME_CADDY2
271#endif
272#define CONFIG_PCI_PNP
273
274#undef CONFIG_EEPRO100
275#undef CONFIG_TULIP
276
277#if !defined(CONFIG_PCI_PNP)
278 #define PCI_ENET0_IOADDR 0xFIXME
279 #define PCI_ENET0_MEMADDR 0xFIXME
280 #define PCI_IDSEL_NUMBER 0xFIXME
281#endif
282
283#define CONFIG_PCI_SCAN_SHOW
284#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
285
286#endif
287
288
289
290
291#ifdef VME_CADDY2
292#else
293#define CONFIG_TSEC_ENET
294#endif
295
296#if defined(CONFIG_TSEC_ENET)
297
298#define CONFIG_GMII
299#define CONFIG_TSEC1
300#define CONFIG_TSEC1_NAME "TSEC0"
301#define CONFIG_TSEC2
302#define CONFIG_TSEC2_NAME "TSEC1"
303#define CONFIG_PHY_M88E1111
304#define TSEC1_PHY_ADDR 0x08
305#define TSEC2_PHY_ADDR 0x10
306#define TSEC1_PHYIDX 0
307#define TSEC2_PHYIDX 0
308#define TSEC1_FLAGS TSEC_GIGABIT
309#define TSEC2_FLAGS TSEC_GIGABIT
310
311
312#define CONFIG_ETHPRIME "TSEC0"
313
314#endif
315
316
317
318
319#ifndef CONFIG_SYS_RAMBOOT
320 #define CONFIG_ENV_IS_IN_FLASH
321 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
322 #define CONFIG_ENV_SECT_SIZE 0x20000
323 #define CONFIG_ENV_SIZE 0x2000
324
325
326#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
327#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
328
329#else
330 #define CONFIG_SYS_NO_FLASH
331 #define CONFIG_ENV_IS_NOWHERE
332 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
333 #define CONFIG_ENV_SIZE 0x2000
334#endif
335
336#define CONFIG_LOADS_ECHO
337#define CONFIG_SYS_LOADS_BAUD_CHANGE
338
339
340
341
342#define CONFIG_BOOTP_BOOTFILESIZE
343#define CONFIG_BOOTP_BOOTPATH
344#define CONFIG_BOOTP_GATEWAY
345#define CONFIG_BOOTP_HOSTNAME
346
347
348
349
350#define CONFIG_CMD_DATE
351#define CONFIG_SYS_RTC_BUS_NUM 0x01
352#define CONFIG_SYS_I2C_RTC_ADDR 0x32
353#define CONFIG_RTC_RX8025
354#define CONFIG_CMD_TSI148
355
356#if defined(CONFIG_PCI)
357 #define CONFIG_CMD_PCI
358#endif
359
360#if defined(CONFIG_SYS_RAMBOOT)
361 #undef CONFIG_CMD_ENV
362#endif
363
364
365#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
366
367#undef CONFIG_WATCHDOG
368
369
370
371
372#define CONFIG_SYS_LONGHELP
373#define CONFIG_SYS_LOAD_ADDR 0x2000000
374
375#if defined(CONFIG_CMD_KGDB)
376 #define CONFIG_SYS_CBSIZE 1024
377#else
378 #define CONFIG_SYS_CBSIZE 256
379#endif
380
381#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
382#define CONFIG_SYS_MAXARGS 16
383#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
384
385
386
387
388
389
390#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
391
392#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
393
394#define CONFIG_SYS_HRCW_LOW (\
395 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
396 HRCWL_DDR_TO_SCB_CLK_1X1 |\
397 HRCWL_CSB_TO_CLKIN |\
398 HRCWL_VCO_1X2 |\
399 HRCWL_CORE_TO_CSB_2X1)
400
401#if defined(PCI_64BIT)
402#define CONFIG_SYS_HRCW_HIGH (\
403 HRCWH_PCI_HOST |\
404 HRCWH_64_BIT_PCI |\
405 HRCWH_PCI1_ARBITER_ENABLE |\
406 HRCWH_PCI2_ARBITER_DISABLE |\
407 HRCWH_CORE_ENABLE |\
408 HRCWH_FROM_0X00000100 |\
409 HRCWH_BOOTSEQ_DISABLE |\
410 HRCWH_SW_WATCHDOG_DISABLE |\
411 HRCWH_ROM_LOC_LOCAL_16BIT |\
412 HRCWH_TSEC1M_IN_GMII |\
413 HRCWH_TSEC2M_IN_GMII)
414#else
415#define CONFIG_SYS_HRCW_HIGH (\
416 HRCWH_PCI_HOST |\
417 HRCWH_32_BIT_PCI |\
418 HRCWH_PCI1_ARBITER_ENABLE |\
419 HRCWH_PCI2_ARBITER_ENABLE |\
420 HRCWH_CORE_ENABLE |\
421 HRCWH_FROM_0X00000100 |\
422 HRCWH_BOOTSEQ_DISABLE |\
423 HRCWH_SW_WATCHDOG_DISABLE |\
424 HRCWH_ROM_LOC_LOCAL_16BIT |\
425 HRCWH_TSEC1M_IN_GMII |\
426 HRCWH_TSEC2M_IN_GMII)
427#endif
428
429
430#define CONFIG_SYS_SICRH 0
431#define CONFIG_SYS_SICRL SICRL_LDP_A
432
433#define CONFIG_SYS_HID0_INIT 0x000000000
434#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
435 HID0_ENABLE_INSTRUCTION_CACHE)
436
437#define CONFIG_SYS_HID2 HID2_HBE
438
439#define CONFIG_SYS_GPIO1_PRELIM
440#define CONFIG_SYS_GPIO1_DIR 0x00100000
441#define CONFIG_SYS_GPIO1_DAT 0x00100000
442
443#define CONFIG_SYS_GPIO2_PRELIM
444#define CONFIG_SYS_GPIO2_DIR 0x78900000
445#define CONFIG_SYS_GPIO2_DAT 0x70100000
446
447#define CONFIG_HIGH_BATS
448
449
450#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
451 BATL_MEMCOHERENCE)
452#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
453 BATU_VS | BATU_VP)
454
455
456#ifdef CONFIG_PCI
457#define CONFIG_PCI_INDIRECT_BRIDGE
458#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
459 BATL_MEMCOHERENCE)
460#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
461 BATU_VS | BATU_VP)
462#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
463 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
464#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
465 BATU_VS | BATU_VP)
466#else
467#define CONFIG_SYS_IBAT1L (0)
468#define CONFIG_SYS_IBAT1U (0)
469#define CONFIG_SYS_IBAT2L (0)
470#define CONFIG_SYS_IBAT2U (0)
471#endif
472
473#ifdef CONFIG_MPC83XX_PCI2
474#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
475 BATL_MEMCOHERENCE)
476#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
477 BATU_VS | BATU_VP)
478#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
479 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
480#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
481 BATU_VS | BATU_VP)
482#else
483#define CONFIG_SYS_IBAT3L (0)
484#define CONFIG_SYS_IBAT3U (0)
485#define CONFIG_SYS_IBAT4L (0)
486#define CONFIG_SYS_IBAT4U (0)
487#endif
488
489
490#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
491 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
492#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
493 BATU_VS | BATU_VP)
494
495#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
496#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
497
498#if (CONFIG_SYS_DDR_SIZE == 512)
499#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
500 BATL_PP_RW | BATL_MEMCOHERENCE)
501#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
502 BATU_BL_256M | BATU_VS | BATU_VP)
503#else
504#define CONFIG_SYS_IBAT7L (0)
505#define CONFIG_SYS_IBAT7U (0)
506#endif
507
508#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
509#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
510#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
511#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
512#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
513#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
514#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
515#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
516#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
517#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
518#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
519#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
520#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
521#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
522#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
523#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
524
525#if defined(CONFIG_CMD_KGDB)
526#define CONFIG_KGDB_BAUDRATE 230400
527#endif
528
529
530
531
532#define CONFIG_ENV_OVERWRITE
533
534#if defined(CONFIG_TSEC_ENET)
535#define CONFIG_HAS_ETH0
536#define CONFIG_HAS_ETH1
537#endif
538
539#define CONFIG_HOSTNAME VME8349
540#define CONFIG_ROOTPATH "/tftpboot/rootfs"
541#define CONFIG_BOOTFILE "uImage"
542
543#define CONFIG_LOADADDR 800000
544
545#undef CONFIG_BOOTARGS
546
547#define CONFIG_BAUDRATE 9600
548
549#define CONFIG_EXTRA_ENV_SETTINGS \
550 "netdev=eth0\0" \
551 "hostname=vme8349\0" \
552 "nfsargs=setenv bootargs root=/dev/nfs rw " \
553 "nfsroot=${serverip}:${rootpath}\0" \
554 "ramargs=setenv bootargs root=/dev/ram rw\0" \
555 "addip=setenv bootargs ${bootargs} " \
556 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
557 ":${hostname}:${netdev}:off panic=1\0" \
558 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
559 "flash_nfs=run nfsargs addip addtty;" \
560 "bootm ${kernel_addr}\0" \
561 "flash_self=run ramargs addip addtty;" \
562 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
563 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
564 "bootm\0" \
565 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
566 "update=protect off fff00000 fff3ffff; " \
567 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
568 "upd=run load update\0" \
569 "fdtaddr=780000\0" \
570 "fdtfile=vme8349.dtb\0" \
571 ""
572
573#define CONFIG_NFSBOOTCOMMAND \
574 "setenv bootargs root=/dev/nfs rw " \
575 "nfsroot=$serverip:$rootpath " \
576 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
577 "$netdev:off " \
578 "console=$consoledev,$baudrate $othbootargs;" \
579 "tftp $loadaddr $bootfile;" \
580 "tftp $fdtaddr $fdtfile;" \
581 "bootm $loadaddr - $fdtaddr"
582
583#define CONFIG_RAMBOOTCOMMAND \
584 "setenv bootargs root=/dev/ram rw " \
585 "console=$consoledev,$baudrate $othbootargs;" \
586 "tftp $ramdiskaddr $ramdiskfile;" \
587 "tftp $loadaddr $bootfile;" \
588 "tftp $fdtaddr $fdtfile;" \
589 "bootm $loadaddr $ramdiskaddr $fdtaddr"
590
591#define CONFIG_BOOTCOMMAND "run flash_self"
592
593#ifndef __ASSEMBLY__
594int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
595 unsigned char *buffer, int len);
596#endif
597
598#endif
599