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14#ifndef __MPC8260_H__
15#define __MPC8260_H__
16
17#ifdef CONFIG_MPC8255
18#define CPU_ID_STR "MPC8255"
19#endif
20#ifndef CPU_ID_STR
21#if defined(CONFIG_MPC8272_FAMILY)
22#ifdef CONFIG_MPC8247
23#define CPU_ID_STR "MPC8247"
24#else
25#define CPU_ID_STR "MPC8272"
26#endif
27#else
28#define CPU_ID_STR "MPC8260"
29#endif
30#endif
31
32
33
34
35#define EXC_OFF_SYS_RESET 0x0100
36#define _START_OFFSET EXC_OFF_SYS_RESET
37
38
39
40
41#define BCR_EBM 0x80000000
42#define BCR_APD_MSK 0x70000000
43#define BCR_L2C 0x08000000
44#define BCR_L2D_MSK 0x07000000
45#define BCR_PLDP 0x00800000
46#define BCR_EAV 0x00400000
47#define BCR_ETM 0x00080000
48#define BCR_LETM 0x00040000
49#define BCR_EPAR 0x00020000
50#define BCR_LEPAR 0x00010000
51#define BCR_NPQM0 0x00008000
52#define BCR_NPQM1 0x00004000
53#define BCR_NPQM2 0x00002000
54#define BCR_EXDD 0x00000400
55#define BCR_ISPS 0x00000010
56
57
58
59
60
61#define PPC_ACR_DBGD 0x20
62#define PPC_ACR_EARB 0x10
63#define PPC_ACR_PRKM_MSK 0x0f
64
65#define PPC_ACR_PRKM_CPMH 0x00
66#define PPC_ACR_PRKM_CPMM 0x01
67#define PPC_ACR_PRKM_CPML 0x02
68#define PPC_ACR_PRKM_CORE 0x06
69#define PPC_ACR_PRKM_EXT1 0x07
70#define PPC_ACR_PRKM_EXT2 0x08
71#define PPC_ACR_PRKM_EXT3 0x09
72
73
74
75
76#define PPC_ALRH_PF0_MSK 0xf0000000
77#define PPC_ALRH_PF1_MSK 0x0f000000
78#define PPC_ALRH_PF2_MSK 0x00f00000
79#define PPC_ALRH_PF3_MSK 0x000f0000
80#define PPC_ALRH_PF4_MSK 0x0000f000
81#define PPC_ALRH_PF5_MSK 0x00000f00
82#define PPC_ALRH_PF6_MSK 0x000000f0
83#define PPC_ALRH_PF7_MSK 0x0000000f
84#define PPC_ALRL_PF8_MSK 0xf0000000
85#define PPC_ALRL_PF9_MSK 0x0f000000
86#define PPC_ALRL_PF10_MSK 0x00f00000
87#define PPC_ALRL_PF11_MSK 0x000f0000
88#define PPC_ALRL_PF12_MSK 0x0000f000
89#define PPC_ALRL_PF13_MSK 0x00000f00
90#define PPC_ALRL_PF14_MSK 0x000000f0
91#define PPC_ALRL_PF15_MSK 0x0000000f
92
93
94
95
96#define LCL_ACR_DBGD 0x20
97#define LCL_ACR_PRKM_MSK 0x0f
98
99#define LCL_ACR_PRKM_CPMH 0x00
100#define LCL_ACR_PRKM_CPMM 0x01
101#define LCL_ACR_PRKM_CPML 0x02
102#define LCL_ACR_PRKM_HOST 0x03
103
104
105
106
107#define LCL_ALRH_PF0_MSK 0xf0000000
108#define LCL_ALRH_PF1_MSK 0x0f000000
109#define LCL_ALRH_PF2_MSK 0x00f00000
110#define LCL_ALRH_PF3_MSK 0x000f0000
111#define LCL_ALRH_PF4_MSK 0x0000f000
112#define LCL_ALRH_PF5_MSK 0x00000f00
113#define LCL_ALRH_PF6_MSK 0x000000f0
114#define LCL_ALRH_PF7_MSK 0x0000000f
115#define LCL_ALRL_PF8_MSK 0xf0000000
116#define LCL_ALRL_PF9_MSK 0x0f000000
117#define LCL_ALRL_PF10_MSK 0x00f00000
118#define LCL_ALRL_PF11_MSK 0x000f0000
119#define LCL_ALRL_PF12_MSK 0x0000f000
120#define LCL_ALRL_PF13_MSK 0x00000f00
121#define LCL_ALRL_PF14_MSK 0x000000f0
122#define LCL_ALRL_PF15_MSK 0x0000000f
123
124
125
126
127#define SIUMCR_BBD 0x80000000
128#define SIUMCR_ESE 0x40000000
129#define SIUMCR_PBSE 0x20000000
130#define SIUMCR_CDIS 0x10000000
131#define SIUMCR_DPPC00 0x00000000
132#define SIUMCR_DPPC01 0x04000000
133#define SIUMCR_DPPC10 0x08000000
134#define SIUMCR_DPPC11 0x0c000000
135#define SIUMCR_L2CPC00 0x00000000
136#define SIUMCR_L2CPC01 0x01000000
137#define SIUMCR_L2CPC10 0x02000000
138#define SIUMCR_L2CPC11 0x03000000
139#define SIUMCR_LBPC00 0x00000000
140#define SIUMCR_LBPC01 0x00400000
141#define SIUMCR_LBPC10 0x00800000
142#define SIUMCR_LBPC11 0x00c00000
143#define SIUMCR_APPC00 0x00000000
144#define SIUMCR_APPC01 0x00100000
145#define SIUMCR_APPC10 0x00200000
146#define SIUMCR_APPC11 0x00300000
147#define SIUMCR_CS10PC00 0x00000000
148#define SIUMCR_CS10PC01 0x00040000
149#define SIUMCR_CS10PC10 0x00080000
150#define SIUMCR_CS10PC11 0x000c0000
151#define SIUMCR_BCTLC00 0x00000000
152#define SIUMCR_BCTLC01 0x00010000
153#define SIUMCR_BCTLC10 0x00020000
154#define SIUMCR_BCTLC11 0x00030000
155#define SIUMCR_MMR00 0x00000000
156#define SIUMCR_MMR01 0x00004000
157#define SIUMCR_MMR10 0x00008000
158#define SIUMCR_MMR11 0x0000c000
159#define SIUMCR_LPBSE 0x00002000
160#define SIUMCR_ABE 0x00000400
161
162
163
164
165#define IMMR_ISB_MSK 0xfffe0000
166#define IMMR_PARTNUM_MSK 0x0000ff00
167#define IMMR_MASKNUM_MSK 0x000000ff
168
169
170
171
172#define SYPCR_SWTC 0xffff0000
173#define SYPCR_BMT 0x0000ff00
174#define SYPCR_PBME 0x00000080
175#define SYPCR_LBME 0x00000040
176#define SYPCR_SWE 0x00000004
177#define SYPCR_SWRI 0x00000002
178#define SYPCR_SWP 0x00000001
179
180
181
182
183#define TMCNTSC_SEC 0x0080
184#define TMCNTSC_ALR 0x0040
185#define TMCNTSC_SIE 0x0008
186#define TMCNTSC_ALE 0x0004
187#define TMCNTSC_TCF 0x0002
188#define TMCNTSC_TCE 0x0001
189
190
191
192
193#if 0
194#define PISCR_PS 0x0080
195#define PISCR_PIE 0x0004
196#define PISCR_PTF 0x0002
197#define PISCR_PTE 0x0001
198#endif
199
200
201
202
203#define RSR_JTRS 0x00000020
204#define RSR_CSRS 0x00000010
205#define RSR_SWRS 0x00000008
206#define RSR_BMRS 0x00000004
207#define RSR_ESRS 0x00000002
208#define RSR_EHRS 0x00000001
209
210#define RSR_ALLBITS (RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS)
211
212
213
214
215#define RMR_CSRE 0x00000001
216
217
218
219
220#define HRCW_EARB 0x80000000
221#define HRCW_EXMC 0x40000000
222#define HRCW_CDIS 0x20000000
223#define HRCW_EBM 0x10000000
224#define HRCW_BPS00 0x00000000
225#define HRCW_BPS01 0x04000000
226#define HRCW_BPS10 0x08000000
227#define HRCW_BPS11 0x0c000000
228#define HRCW_CIP 0x02000000
229#define HRCW_ISPS 0x01000000
230#define HRCW_L2CPC00 0x00000000
231#define HRCW_L2CPC01 0x00400000
232#define HRCW_L2CPC10 0x00800000
233#define HRCW_L2CPC11 0x00c00000
234#define HRCW_DPPC00 0x00000000
235#define HRCW_DPPC01 0x00100000
236#define HRCW_DPPC10 0x00200000
237#define HRCW_DPPC11 0x00300000
238#define HRCW_reserved1 0x00080000
239#define HRCW_ISB000 0x00000000
240#define HRCW_ISB001 0x00010000
241#define HRCW_ISB010 0x00020000
242#define HRCW_ISB011 0x00030000
243#define HRCW_ISB100 0x00040000
244#define HRCW_ISB101 0x00050000
245#define HRCW_ISB110 0x00060000
246#define HRCW_ISB111 0x00070000
247#define HRCW_BMS 0x00008000
248#define HRCW_BBD 0x00004000
249#define HRCW_MMR00 0x00000000
250#define HRCW_MMR01 0x00001000
251#define HRCW_MMR10 0x00002000
252#define HRCW_MMR11 0x00003000
253#define HRCW_LBPC00 0x00000000
254#define HRCW_LBPC01 0x00000400
255#define HRCW_LBPC10 0x00000800
256#define HRCW_LBPC11 0x00000c00
257#define HRCW_APPC00 0x00000000
258#define HRCW_APPC01 0x00000100
259#define HRCW_APPC10 0x00000200
260#define HRCW_APPC11 0x00000300
261#define HRCW_CS10PC00 0x00000000
262#define HRCW_CS10PC01 0x00000040
263#define HRCW_CS10PC10 0x00000080
264#define HRCW_CS10PC11 0x000000c0
265#define HRCW_MODCK_H0000 0x00000000
266#define HRCW_MODCK_H0001 0x00000001
267#define HRCW_MODCK_H0010 0x00000002
268#define HRCW_MODCK_H0011 0x00000003
269#define HRCW_MODCK_H0100 0x00000004
270#define HRCW_MODCK_H0101 0x00000005
271#define HRCW_MODCK_H0110 0x00000006
272#define HRCW_MODCK_H0111 0x00000007
273#define HRCW_MODCK_H1000 0x00000008
274#define HRCW_MODCK_H1001 0x00000009
275#define HRCW_MODCK_H1010 0x0000000a
276#define HRCW_MODCK_H1011 0x0000000b
277#define HRCW_MODCK_H1100 0x0000000c
278#define HRCW_MODCK_H1101 0x0000000d
279#define HRCW_MODCK_H1110 0x0000000e
280#define HRCW_MODCK_H1111 0x0000000f
281
282
283
284
285#define SCCR_PCI_MODE 0x00000100
286#define SCCR_PCI_MODCK 0x00000080
287#define SCCR_PCIDF_MSK 0x00000078
288#define SCCR_PCIDF_SHIFT 3
289#define SCCR_CLPD 0x00000004
290#define SCCR_DFBRG_MSK 0x00000003
291#define SCCR_DFBRG_SHIFT 0
292
293#define SCCR_DFBRG00 0x00000000
294#define SCCR_DFBRG01 0x00000001
295#define SCCR_DFBRG10 0x00000002
296#define SCCR_DFBRG11 0x00000003
297
298
299
300
301#define SCMR_CORECNF_MSK 0x1f000000
302#define SCMR_CORECNF_SHIFT 24
303#define SCMR_BUSDF_MSK 0x00f00000
304#define SCMR_BUSDF_SHIFT 20
305#define SCMR_CPMDF_MSK 0x000f0000
306#define SCMR_CPMDF_SHIFT 16
307#define SCMR_PLLDF 0x00001000
308#define SCMR_PLLMF_MSK 0x00000fff
309#define SCMR_PLLMF_MSKH7 0x0000000f
310#define SCMR_PLLMF_SHIFT 0
311
312
313
314
315
316#define MxMR_BSEL 0x80000000
317#define MxMR_RFEN 0x40000000
318#define MxMR_OP_MSK 0x30000000
319#define MxMR_AMx_MSK 0x07000000
320#define MxMR_DSx_MSK 0x00c00000
321#define MxMR_G0CLx_MSK 0x00380000
322#define MxMR_GPL_x4DIS 0x00040000
323#define MxMR_RLFx_MSK 0x0003c000
324#define MxMR_WLFx_MSK 0x00003c00
325#define MxMR_TLFx_MSK 0x000003c0
326#define MxMR_MAD_MSK 0x0000003f
327
328#define MxMR_OP_NORM 0x00000000
329#define MxMR_OP_WARR 0x10000000
330#define MxMR_OP_RARR 0x20000000
331#define MxMR_OP_RUNP 0x30000000
332
333#define MxMR_AMx_TYPE_0 0x00000000
334#define MxMR_AMx_TYPE_1 0x01000000
335#define MxMR_AMx_TYPE_2 0x02000000
336#define MxMR_AMx_TYPE_3 0x03000000
337#define MxMR_AMx_TYPE_4 0x04000000
338#define MxMR_AMx_TYPE_5 0x05000000
339
340#define MxMR_DSx_1_CYCL 0x00000000
341#define MxMR_DSx_2_CYCL 0x00400000
342#define MxMR_DSx_3_CYCL 0x00800000
343#define MxMR_DSx_4_CYCL 0x00c00000
344
345#define MxMR_G0CLx_A12 0x00000000
346#define MxMR_G0CLx_A11 0x00080000
347#define MxMR_G0CLx_A10 0x00100000
348#define MxMR_G0CLx_A9 0x00180000
349#define MxMR_G0CLx_A8 0x00200000
350#define MxMR_G0CLx_A7 0x00280000
351#define MxMR_G0CLx_A6 0x00300000
352#define MxMR_G0CLx_A5 0x00380000
353
354#define MxMR_RLFx_1X 0x00004000
355#define MxMR_RLFx_2X 0x00008000
356#define MxMR_RLFx_3X 0x0000c000
357#define MxMR_RLFx_4X 0x00010000
358#define MxMR_RLFx_5X 0x00014000
359#define MxMR_RLFx_6X 0x00018000
360#define MxMR_RLFx_7X 0x0001c000
361#define MxMR_RLFx_8X 0x00020000
362#define MxMR_RLFx_9X 0x00024000
363#define MxMR_RLFx_10X 0x00028000
364#define MxMR_RLFx_11X 0x0002c000
365#define MxMR_RLFx_12X 0x00030000
366#define MxMR_RLFx_13X 0x00034000
367#define MxMR_RLFx_14X 0x00038000
368#define MxMR_RLFx_15X 0x0003c000
369#define MxMR_RLFx_16X 0x00000000
370
371#define MxMR_WLFx_1X 0x00000400
372#define MxMR_WLFx_2X 0x00000800
373#define MxMR_WLFx_3X 0x00000c00
374#define MxMR_WLFx_4X 0x00001000
375#define MxMR_WLFx_5X 0x00001400
376#define MxMR_WLFx_6X 0x00001800
377#define MxMR_WLFx_7X 0x00001c00
378#define MxMR_WLFx_8X 0x00002000
379#define MxMR_WLFx_9X 0x00002400
380#define MxMR_WLFx_10X 0x00002800
381#define MxMR_WLFx_11X 0x00002c00
382#define MxMR_WLFx_12X 0x00003000
383#define MxMR_WLFx_13X 0x00003400
384#define MxMR_WLFx_14X 0x00003800
385#define MxMR_WLFx_15X 0x00003c00
386#define MxMR_WLFx_16X 0x00000000
387
388#define MxMR_TLFx_1X 0x00000040
389#define MxMR_TLFx_2X 0x00000080
390#define MxMR_TLFx_3X 0x000000c0
391#define MxMR_TLFx_4X 0x00000100
392#define MxMR_TLFx_5X 0x00000140
393#define MxMR_TLFx_6X 0x00000180
394#define MxMR_TLFx_7X 0x000001c0
395#define MxMR_TLFx_8X 0x00000200
396#define MxMR_TLFx_9X 0x00000240
397#define MxMR_TLFx_10X 0x00000280
398#define MxMR_TLFx_11X 0x000002c0
399#define MxMR_TLFx_12X 0x00000300
400#define MxMR_TLFx_13X 0x00000340
401#define MxMR_TLFx_14X 0x00000380
402#define MxMR_TLFx_15X 0x000003c0
403#define MxMR_TLFx_16X 0x00000000
404
405
406
407
408
409#define BRx_BA_MSK 0xffff8000
410#define BRx_PS_MSK 0x00001800
411#define BRx_DECC_MSK 0x00000600
412#define BRx_WP 0x00000100
413#define BRx_MS_MSK 0x000000e0
414#define BRx_EMEMC 0x00000010
415#define BRx_ATOM_MSK 0x0000000c
416#define BRx_DR 0x00000002
417#define BRx_V 0x00000001
418
419#define BRx_PS_64 0x00000000
420#define BRx_PS_8 0x00000800
421#define BRx_PS_16 0x00001000
422#define BRx_PS_32 0x00001800
423
424#define BRx_DECC_NONE 0x00000000
425#define BRx_DECC_NORMAL 0x00000200
426#define BRx_DECC_RMWPC 0x00000400
427#define BRx_DECC_ECC 0x00000600
428
429#define BRx_MS_GPCM_P 0x00000000
430#define BRx_MS_GPCM_L 0x00000020
431#define BRx_MS_SDRAM_P 0x00000040
432#define BRx_MS_SDRAM_L 0x00000060
433#define BRx_MS_UPMA 0x00000080
434#define BRx_MS_UPMB 0x000000a0
435#define BRx_MS_UPMC 0x000000c0
436
437#define BRx_ATOM_RAWA 0x00000004
438#define BRx_ATOM_WARA 0x00000008
439
440
441
442
443#define ORxS_SDAM_MSK 0xfff00000
444#define ORxS_LSDAM_MSK 0x000f8000
445#define ORxS_BPD_MSK 0x00006000
446#define ORxS_ROWST_MSK 0x00001e00
447#define ORxS_NUMR_MSK 0x000001c0
448#define ORxS_PMSEL 0x00000020
449#define ORxS_IBID 0x00000010
450
451#define ORxS_BPD_2 0x00000000
452#define ORxS_BPD_4 0x00002000
453#define ORxS_BPD_8 0x00004000
454
455
456#define ORxS_ROWST_PBI0_A7 0x00000400
457#define ORxS_ROWST_PBI0_A8 0x00000800
458#define ORxS_ROWST_PBI0_A9 0x00000c00
459#define ORxS_ROWST_PBI0_A10 0x00001000
460#define ORxS_ROWST_PBI0_A11 0x00001400
461#define ORxS_ROWST_PBI0_A12 0x00001800
462#define ORxS_ROWST_PBI0_A13 0x00001c00
463
464
465#define ORxS_ROWST_PBI1_A0 0x00000000
466#define ORxS_ROWST_PBI1_A1 0x00000200
467#define ORxS_ROWST_PBI1_A2 0x00000400
468#define ORxS_ROWST_PBI1_A3 0x00000600
469#define ORxS_ROWST_PBI1_A4 0x00000800
470#define ORxS_ROWST_PBI1_A5 0x00000a00
471#define ORxS_ROWST_PBI1_A6 0x00000c00
472#define ORxS_ROWST_PBI1_A7 0x00000e00
473#define ORxS_ROWST_PBI1_A8 0x00001000
474#define ORxS_ROWST_PBI1_A9 0x00001200
475#define ORxS_ROWST_PBI1_A10 0x00001400
476#define ORxS_ROWST_PBI1_A11 0x00001600
477#define ORxS_ROWST_PBI1_A12 0x00001800
478
479#define ORxS_NUMR_9 0x00000000
480#define ORxS_NUMR_10 0x00000040
481#define ORxS_NUMR_11 0x00000080
482#define ORxS_NUMR_12 0x000000c0
483#define ORxS_NUMR_13 0x00000100
484#define ORxS_NUMR_14 0x00000140
485#define ORxS_NUMR_15 0x00000180
486#define ORxS_NUMR_16 0x000001c0
487
488
489#define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000)
490
491
492
493
494#define ORxG_AM_MSK 0xffff8000
495#define ORxG_BCTLD 0x00001000
496#define ORxG_CSNT 0x00000800
497#define ORxG_ACS_MSK 0x00000600
498#define ORxG_SCY_MSK 0x000000f0
499#define ORxG_SETA 0x00000008
500#define ORxG_TRLX 0x00000004
501#define ORxG_EHTR 0x00000002
502
503#define ORxG_ACS_DIV1 0x00000000
504#define ORxG_ACS_DIV4 0x00000400
505#define ORxG_ACS_DIV2 0x00000600
506
507#define ORxG_SCY_0_CLK 0x00000000
508#define ORxG_SCY_1_CLK 0x00000010
509#define ORxG_SCY_2_CLK 0x00000020
510#define ORxG_SCY_3_CLK 0x00000030
511#define ORxG_SCY_4_CLK 0x00000040
512#define ORxG_SCY_5_CLK 0x00000050
513#define ORxG_SCY_6_CLK 0x00000060
514#define ORxG_SCY_7_CLK 0x00000070
515#define ORxG_SCY_8_CLK 0x00000080
516#define ORxG_SCY_9_CLK 0x00000090
517#define ORxG_SCY_10_CLK 0x000000a0
518#define ORxG_SCY_11_CLK 0x000000b0
519#define ORxG_SCY_12_CLK 0x000000c0
520#define ORxG_SCY_13_CLK 0x000000d0
521#define ORxG_SCY_14_CLK 0x000000e0
522#define ORxG_SCY_15_CLK 0x000000f0
523
524
525
526
527#define ORxU_AM_MSK 0xffff8000
528#define ORxU_BCTLD 0x00001000
529#define ORxU_BI 0x00000100
530#define ORxU_EHTR_MSK 0x00000006
531
532#define ORxU_EHTR_NORM 0x00000000
533#define ORxU_EHTR_1IDLE 0x00000002
534#define ORxU_EHTR_4IDLE 0x00000004
535#define ORxU_EHTR_8IDLE 0x00000006
536
537
538
539#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000)
540#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
541
542
543
544
545
546#define PSDMR_PBI 0x80000000
547#define PSDMR_RFEN 0x40000000
548#define PSDMR_OP_MSK 0x38000000
549#define PSDMR_SDAM_MSK 0x07000000
550#define PSDMR_BSMA_MSK 0x00e00000
551#define PSDMR_SDA10_MSK 0x001c0000
552#define PSDMR_RFRC_MSK 0x00038000
553#define PSDMR_PRETOACT_MSK 0x00007000
554#define PSDMR_ACTTORW_MSK 0x00000e00
555#define PSDMR_BL 0x00000100
556#define PSDMR_LDOTOPRE_MSK 0x000000c0
557#define PSDMR_WRC_MSK 0x00000030
558#define PSDMR_EAMUX 0x00000008
559#define PSDMR_BUFCMD 0x00000004
560#define PSDMR_CL_MSK 0x00000003
561
562#define PSDMR_OP_NORM 0x00000000
563#define PSDMR_OP_CBRR 0x08000000
564#define PSDMR_OP_SELFR 0x10000000
565#define PSDMR_OP_MRW 0x18000000
566#define PSDMR_OP_PREB 0x20000000
567#define PSDMR_OP_PREA 0x28000000
568#define PSDMR_OP_ACTB 0x30000000
569#define PSDMR_OP_RW 0x38000000
570
571#define PSDMR_SDAM_A13_IS_A5 0x00000000
572#define PSDMR_SDAM_A14_IS_A5 0x01000000
573#define PSDMR_SDAM_A15_IS_A5 0x02000000
574#define PSDMR_SDAM_A16_IS_A5 0x03000000
575#define PSDMR_SDAM_A17_IS_A5 0x04000000
576#define PSDMR_SDAM_A18_IS_A5 0x05000000
577
578#define PSDMR_BSMA_A12_A14 0x00000000
579#define PSDMR_BSMA_A13_A15 0x00200000
580#define PSDMR_BSMA_A14_A16 0x00400000
581#define PSDMR_BSMA_A15_A17 0x00600000
582#define PSDMR_BSMA_A16_A18 0x00800000
583#define PSDMR_BSMA_A17_A19 0x00a00000
584#define PSDMR_BSMA_A18_A20 0x00c00000
585#define PSDMR_BSMA_A19_A21 0x00e00000
586
587
588#define PSDMR_SDA10_PBI0_A12 0x00000000
589#define PSDMR_SDA10_PBI0_A11 0x00040000
590#define PSDMR_SDA10_PBI0_A10 0x00080000
591#define PSDMR_SDA10_PBI0_A9 0x000c0000
592#define PSDMR_SDA10_PBI0_A8 0x00100000
593#define PSDMR_SDA10_PBI0_A7 0x00140000
594#define PSDMR_SDA10_PBI0_A6 0x00180000
595#define PSDMR_SDA10_PBI0_A5 0x001c0000
596
597
598#define PSDMR_SDA10_PBI1_A10 0x00000000
599#define PSDMR_SDA10_PBI1_A9 0x00040000
600#define PSDMR_SDA10_PBI1_A8 0x00080000
601#define PSDMR_SDA10_PBI1_A7 0x000c0000
602#define PSDMR_SDA10_PBI1_A6 0x00100000
603#define PSDMR_SDA10_PBI1_A5 0x00140000
604#define PSDMR_SDA10_PBI1_A4 0x00180000
605#define PSDMR_SDA10_PBI1_A3 0x001c0000
606
607#define PSDMR_RFRC_3_CLK 0x00008000
608#define PSDMR_RFRC_4_CLK 0x00010000
609#define PSDMR_RFRC_5_CLK 0x00018000
610#define PSDMR_RFRC_6_CLK 0x00020000
611#define PSDMR_RFRC_7_CLK 0x00028000
612#define PSDMR_RFRC_8_CLK 0x00030000
613#define PSDMR_RFRC_16_CLK 0x00038000
614
615#define PSDMR_PRETOACT_8W 0x00000000
616#define PSDMR_PRETOACT_1W 0x00001000
617#define PSDMR_PRETOACT_2W 0x00002000
618#define PSDMR_PRETOACT_3W 0x00003000
619#define PSDMR_PRETOACT_4W 0x00004000
620#define PSDMR_PRETOACT_5W 0x00005000
621#define PSDMR_PRETOACT_6W 0x00006000
622#define PSDMR_PRETOACT_7W 0x00007000
623
624#define PSDMR_ACTTORW_8W 0x00000000
625#define PSDMR_ACTTORW_1W 0x00000200
626#define PSDMR_ACTTORW_2W 0x00000400
627#define PSDMR_ACTTORW_3W 0x00000600
628#define PSDMR_ACTTORW_4W 0x00000800
629#define PSDMR_ACTTORW_5W 0x00000a00
630#define PSDMR_ACTTORW_6W 0x00000c00
631#define PSDMR_ACTTORW_7W 0x00000e00
632
633#define PSDMR_LDOTOPRE_0C 0x00000000
634#define PSDMR_LDOTOPRE_1C 0x00000040
635#define PSDMR_LDOTOPRE_2C 0x00000080
636
637#define PSDMR_WRC_4C 0x00000000
638#define PSDMR_WRC_1C 0x00000010
639#define PSDMR_WRC_2C 0x00000020
640#define PSDMR_WRC_3C 0x00000030
641
642#define PSDMR_CL_1 0x00000001
643#define PSDMR_CL_2 0x00000002
644#define PSDMR_CL_3 0x00000003
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661#define MPTPR_PTP_MSK 0xff00
662#define MPTPR_PTP_DIV2 0x2000
663#define MPTPR_PTP_DIV4 0x1000
664#define MPTPR_PTP_DIV8 0x0800
665#define MPTPR_PTP_DIV16 0x0400
666#define MPTPR_PTP_DIV32 0x0200
667#define MPTPR_PTP_DIV64 0x0100
668
669
670
671
672
673#define TGCR1_CAS2 0x80
674#define TGCR1_STP2 0x20
675#define TGCR1_RST2 0x10
676#define TGCR1_GM1 0x08
677#define TGCR1_STP1 0x02
678#define TGCR1_RST1 0x01
679#define TGCR2_CAS4 0x80
680#define TGCR2_STP4 0x20
681#define TGCR2_RST4 0x10
682#define TGCR2_GM2 0x08
683#define TGCR2_STP3 0x02
684#define TGCR2_RST3 0x01
685
686
687
688
689
690#define TMRx_PS_MSK 0xff00
691#define TMRx_CE_MSK 0x00c0
692#define TMRx_OM 0x0020
693#define TMRx_ORI 0x0010
694#define TMRx_FRR 0x0008
695#define TMRx_ICLK_MSK 0x0006
696#define TMRx_GE 0x0001
697
698#define TMRx_CE_INTR_DIS 0x0000
699#define TMRx_CE_RISING 0x0040
700#define TMRx_CE_FALLING 0x0080
701#define TMRx_CE_ANY 0x00c0
702
703#define TMRx_ICLK_IN_CAS 0x0000
704#define TMRx_ICLK_IN_GEN 0x0002
705#define TMRx_ICLK_IN_GEN_DIV16 0x0004
706#define TMRx_ICLK_TIN_PIN 0x0006
707
708
709
710
711
712#define CMXFCR_FC1 0x40000000
713#define CMXFCR_RF1CS_MSK 0x38000000
714#define CMXFCR_TF1CS_MSK 0x07000000
715#define CMXFCR_FC2 0x00400000
716#define CMXFCR_RF2CS_MSK 0x00380000
717#define CMXFCR_TF2CS_MSK 0x00070000
718#define CMXFCR_FC3 0x00004000
719#define CMXFCR_RF3CS_MSK 0x00003800
720#define CMXFCR_TF3CS_MSK 0x00000700
721
722#define CMXFCR_RF1CS_BRG5 0x00000000
723#define CMXFCR_RF1CS_BRG6 0x08000000
724#define CMXFCR_RF1CS_BRG7 0x10000000
725#define CMXFCR_RF1CS_BRG8 0x18000000
726#define CMXFCR_RF1CS_CLK9 0x20000000
727#define CMXFCR_RF1CS_CLK10 0x28000000
728#define CMXFCR_RF1CS_CLK11 0x30000000
729#define CMXFCR_RF1CS_CLK12 0x38000000
730
731#define CMXFCR_TF1CS_BRG5 0x00000000
732#define CMXFCR_TF1CS_BRG6 0x01000000
733#define CMXFCR_TF1CS_BRG7 0x02000000
734#define CMXFCR_TF1CS_BRG8 0x03000000
735#define CMXFCR_TF1CS_CLK9 0x04000000
736#define CMXFCR_TF1CS_CLK10 0x05000000
737#define CMXFCR_TF1CS_CLK11 0x06000000
738#define CMXFCR_TF1CS_CLK12 0x07000000
739
740#define CMXFCR_RF2CS_BRG5 0x00000000
741#define CMXFCR_RF2CS_BRG6 0x00080000
742#define CMXFCR_RF2CS_BRG7 0x00100000
743#define CMXFCR_RF2CS_BRG8 0x00180000
744#define CMXFCR_RF2CS_CLK13 0x00200000
745#define CMXFCR_RF2CS_CLK14 0x00280000
746#define CMXFCR_RF2CS_CLK15 0x00300000
747#define CMXFCR_RF2CS_CLK16 0x00380000
748
749#define CMXFCR_TF2CS_BRG5 0x00000000
750#define CMXFCR_TF2CS_BRG6 0x00010000
751#define CMXFCR_TF2CS_BRG7 0x00020000
752#define CMXFCR_TF2CS_BRG8 0x00030000
753#define CMXFCR_TF2CS_CLK13 0x00040000
754#define CMXFCR_TF2CS_CLK14 0x00050000
755#define CMXFCR_TF2CS_CLK15 0x00060000
756#define CMXFCR_TF2CS_CLK16 0x00070000
757
758#define CMXFCR_RF3CS_BRG5 0x00000000
759#define CMXFCR_RF3CS_BRG6 0x00000800
760#define CMXFCR_RF3CS_BRG7 0x00001000
761#define CMXFCR_RF3CS_BRG8 0x00001800
762#define CMXFCR_RF3CS_CLK13 0x00002000
763#define CMXFCR_RF3CS_CLK14 0x00002800
764#define CMXFCR_RF3CS_CLK15 0x00003000
765#define CMXFCR_RF3CS_CLK16 0x00003800
766
767#define CMXFCR_TF3CS_BRG5 0x00000000
768#define CMXFCR_TF3CS_BRG6 0x00000100
769#define CMXFCR_TF3CS_BRG7 0x00000200
770#define CMXFCR_TF3CS_BRG8 0x00000300
771#define CMXFCR_TF3CS_CLK13 0x00000400
772#define CMXFCR_TF3CS_CLK14 0x00000500
773#define CMXFCR_TF3CS_CLK15 0x00000600
774#define CMXFCR_TF3CS_CLK16 0x00000700
775
776
777
778
779#define CMXSCR_GR1 0x80000000
780#define CMXSCR_SC1 0x40000000
781#define CMXSCR_RS1CS_MSK 0x38000000
782#define CMXSCR_TS1CS_MSK 0x07000000
783#define CMXSCR_GR2 0x00800000
784#define CMXSCR_SC2 0x00400000
785#define CMXSCR_RS2CS_MSK 0x00380000
786#define CMXSCR_TS2CS_MSK 0x00070000
787#define CMXSCR_GR3 0x00008000
788#define CMXSCR_SC3 0x00004000
789#define CMXSCR_RS3CS_MSK 0x00003800
790#define CMXSCR_TS3CS_MSK 0x00000700
791#define CMXSCR_GR4 0x00000080
792#define CMXSCR_SC4 0x00000040
793#define CMXSCR_RS4CS_MSK 0x00000038
794#define CMXSCR_TS4CS_MSK 0x00000007
795
796#define CMXSCR_RS1CS_BRG1 0x00000000
797#define CMXSCR_RS1CS_BRG2 0x08000000
798#define CMXSCR_RS1CS_BRG3 0x10000000
799#define CMXSCR_RS1CS_BRG4 0x18000000
800#define CMXSCR_RS1CS_CLK11 0x20000000
801#define CMXSCR_RS1CS_CLK12 0x28000000
802#define CMXSCR_RS1CS_CLK3 0x30000000
803#define CMXSCR_RS1CS_CLK4 0x38000000
804
805#define CMXSCR_TS1CS_BRG1 0x00000000
806#define CMXSCR_TS1CS_BRG2 0x01000000
807#define CMXSCR_TS1CS_BRG3 0x02000000
808#define CMXSCR_TS1CS_BRG4 0x03000000
809#define CMXSCR_TS1CS_CLK11 0x04000000
810#define CMXSCR_TS1CS_CLK12 0x05000000
811#define CMXSCR_TS1CS_CLK3 0x06000000
812#define CMXSCR_TS1CS_CLK4 0x07000000
813
814#define CMXSCR_RS2CS_BRG1 0x00000000
815#define CMXSCR_RS2CS_BRG2 0x00080000
816#define CMXSCR_RS2CS_BRG3 0x00100000
817#define CMXSCR_RS2CS_BRG4 0x00180000
818#define CMXSCR_RS2CS_CLK11 0x00200000
819#define CMXSCR_RS2CS_CLK12 0x00280000
820#define CMXSCR_RS2CS_CLK3 0x00300000
821#define CMXSCR_RS2CS_CLK4 0x00380000
822
823#define CMXSCR_TS2CS_BRG1 0x00000000
824#define CMXSCR_TS2CS_BRG2 0x00010000
825#define CMXSCR_TS2CS_BRG3 0x00020000
826#define CMXSCR_TS2CS_BRG4 0x00030000
827#define CMXSCR_TS2CS_CLK11 0x00040000
828#define CMXSCR_TS2CS_CLK12 0x00050000
829#define CMXSCR_TS2CS_CLK3 0x00060000
830#define CMXSCR_TS2CS_CLK4 0x00070000
831
832#define CMXSCR_RS3CS_BRG1 0x00000000
833#define CMXSCR_RS3CS_BRG2 0x00000800
834#define CMXSCR_RS3CS_BRG3 0x00001000
835#define CMXSCR_RS3CS_BRG4 0x00001800
836#define CMXSCR_RS3CS_CLK5 0x00002000
837#define CMXSCR_RS3CS_CLK6 0x00002800
838#define CMXSCR_RS3CS_CLK7 0x00003000
839#define CMXSCR_RS3CS_CLK8 0x00003800
840
841#define CMXSCR_TS3CS_BRG1 0x00000000
842#define CMXSCR_TS3CS_BRG2 0x00000100
843#define CMXSCR_TS3CS_BRG3 0x00000200
844#define CMXSCR_TS3CS_BRG4 0x00000300
845#define CMXSCR_TS3CS_CLK5 0x00000400
846#define CMXSCR_TS3CS_CLK6 0x00000500
847#define CMXSCR_TS3CS_CLK7 0x00000600
848#define CMXSCR_TS3CS_CLK8 0x00000700
849
850#define CMXSCR_RS4CS_BRG1 0x00000000
851#define CMXSCR_RS4CS_BRG2 0x00000008
852#define CMXSCR_RS4CS_BRG3 0x00000010
853#define CMXSCR_RS4CS_BRG4 0x00000018
854#define CMXSCR_RS4CS_CLK5 0x00000020
855#define CMXSCR_RS4CS_CLK6 0x00000028
856#define CMXSCR_RS4CS_CLK7 0x00000030
857#define CMXSCR_RS4CS_CLK8 0x00000038
858
859#define CMXSCR_TS4CS_BRG1 0x00000000
860#define CMXSCR_TS4CS_BRG2 0x00000001
861#define CMXSCR_TS4CS_BRG3 0x00000002
862#define CMXSCR_TS4CS_BRG4 0x00000003
863#define CMXSCR_TS4CS_CLK5 0x00000004
864#define CMXSCR_TS4CS_CLK6 0x00000005
865#define CMXSCR_TS4CS_CLK7 0x00000006
866#define CMXSCR_TS4CS_CLK8 0x00000007
867
868
869
870
871#define CMXSMR_SMC1 0x80
872#define CMXSMR_SMC1CS_MSK 0x30
873#define CMXSMR_SMC2 0x08
874#define CMXSMR_SMC2CS_MSK 0x03
875
876#define CMXSMR_SMC1CS_BRG1 0x00
877#define CMXSMR_SMC1CS_BRG7 0x10
878#define CMXSMR_SMC1CS_CLK7 0x20
879#define CMXSMR_SMC1CS_CLK9 0x30
880
881#define CMXSMR_SMC2CS_BRG2 0x00
882#define CMXSMR_SMC2CS_BRG8 0x01
883#define CMXSMR_SMC2CS_CLK19 0x02
884#define CMXSMR_SMC2CS_CLK20 0x03
885
886
887
888
889
890#define UPMA 1
891#define UPMB 2
892#define UPMC 3
893
894#if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG)
895static __inline__ void
896reset_8260_watchdog(volatile immap_t *immr)
897{
898 immr->im_siu_conf.sc_swsr = 0x556c;
899 immr->im_siu_conf.sc_swsr = 0xaa39;
900}
901#endif
902
903#endif
904