LXR uboot/arch/arm/include/asm/arch-am33xx/cpu.h

   1/*
   2 * cpu.h
   3 *
   4 * AM33xx specific header file
   5 *
   6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11#ifndef _AM33XX_CPU_H
  12#define _AM33XX_CPU_H
  13
  14#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  15#include <asm/types.h>
  16#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  17
  18#include <asm/arch/hardware.h>
  19
  20#define CL_BIT(x)                       (0 << x)
  21
  22/* Timer register bits */
  23#define TCLR_ST                         BIT(0)  /* Start=1 Stop=0 */
  24#define TCLR_AR                         BIT(1)  /* Auto reload */
  25#define TCLR_PRE                        BIT(5)  /* Pre-scaler enable */
  26#define TCLR_PTV_SHIFT                  (2)     /* Pre-scaler shift value */
  27#define TCLR_PRE_DISABLE                CL_BIT(5) /* Pre-scalar disable */
  28#define TCLR_CE                         BIT(6)  /* compare mode enable */
  29#define TCLR_SCPWM                      BIT(7)  /* pwm outpin behaviour */
  30#define TCLR_TCM                        BIT(8)  /* edge detection of input pin*/
  31#define TCLR_TRG_SHIFT                  (10)    /* trigmode on pwm outpin */
  32#define TCLR_PT                         BIT(12) /* pulse/toggle mode of outpin*/
  33#define TCLR_CAPTMODE                   BIT(13) /* capture mode */
  34#define TCLR_GPOCFG                     BIT(14) /* 0=output,1=input */
  35
  36#define TCFG_RESET                      BIT(0)  /* software reset */
  37#define TCFG_EMUFREE                    BIT(1)  /* behaviour of tmr on debug */
  38#define TCFG_IDLEMOD_SHIFT              (2)     /* power management */
  39/* device type */
  40#define DEVICE_MASK                     (BIT(8) | BIT(9) | BIT(10))
  41#define TST_DEVICE                      0x0
  42#define EMU_DEVICE                      0x1
  43#define HS_DEVICE                       0x2
  44#define GP_DEVICE                       0x3
  45
  46/* cpu-id for AM33XX and TI81XX family */
  47#define AM335X                          0xB944
  48#define TI81XX                          0xB81E
  49#define DEVICE_ID                       (CTRL_BASE + 0x0600)
  50#define DEVICE_ID_MASK                  0x1FFF
  51
  52/* MPU max frequencies */
  53#define AM335X_ZCZ_300                  0x1FEF
  54#define AM335X_ZCZ_600                  0x1FAF
  55#define AM335X_ZCZ_720                  0x1F2F
  56#define AM335X_ZCZ_800                  0x1E2F
  57#define AM335X_ZCZ_1000                 0x1C2F
  58#define AM335X_ZCE_300                  0x1FDF
  59#define AM335X_ZCE_600                  0x1F9F
  60
  61/* This gives the status of the boot mode pins on the evm */
  62#define SYSBOOT_MASK                    (BIT(0) | BIT(1) | BIT(2)\
  63                                        | BIT(3) | BIT(4))
  64
  65#define PRM_RSTCTRL_RESET               0x01
  66#define PRM_RSTST_WARM_RESET_MASK       0x232
  67
  68/*
  69 * Watchdog:
  70 * Using the prescaler, the OMAP watchdog could go for many
  71 * months before firing.  These limits work without scaling,
  72 * with the 60 second default assumed by most tools and docs.
  73 */
  74#define TIMER_MARGIN_MAX        (24 * 60 * 60)  /* 1 day */
  75#define TIMER_MARGIN_DEFAULT    60      /* 60 secs */
  76#define TIMER_MARGIN_MIN        1
  77
  78#define PTV                     0       /* prescale */
  79#define GET_WLDR_VAL(secs)      (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
  80#define WDT_WWPS_PEND_WCLR      BIT(0)
  81#define WDT_WWPS_PEND_WLDR      BIT(2)
  82#define WDT_WWPS_PEND_WTGR      BIT(3)
  83#define WDT_WWPS_PEND_WSPR      BIT(4)
  84
  85#define WDT_WCLR_PRE            BIT(5)
  86#define WDT_WCLR_PTV_OFF        2
  87
  88#ifndef __KERNEL_STRICT_NAMES
  89#ifndef __ASSEMBLY__
  90
  91
  92#ifndef CONFIG_AM43XX
  93/* Encapsulating core pll registers */
  94struct cm_wkuppll {
  95        unsigned int wkclkstctrl;       /* offset 0x00 */
  96        unsigned int wkctrlclkctrl;     /* offset 0x04 */
  97        unsigned int wkgpio0clkctrl;    /* offset 0x08 */
  98        unsigned int wkl4wkclkctrl;     /* offset 0x0c */
  99        unsigned int timer0clkctrl;     /* offset 0x10 */
 100        unsigned int resv2[3];
 101        unsigned int idlestdpllmpu;     /* offset 0x20 */
 102        unsigned int sscdeltamstepdllmpu; /* off  0x24 */
 103        unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
 104        unsigned int clkseldpllmpu;     /* offset 0x2c */
 105        unsigned int resv4[1];
 106        unsigned int idlestdpllddr;     /* offset 0x34 */
 107        unsigned int resv5[2];
 108        unsigned int clkseldpllddr;     /* offset 0x40 */
 109        unsigned int resv6[4];
 110        unsigned int clkseldplldisp;    /* offset 0x54 */
 111        unsigned int resv7[1];
 112        unsigned int idlestdpllcore;    /* offset 0x5c */
 113        unsigned int resv8[2];
 114        unsigned int clkseldpllcore;    /* offset 0x68 */
 115        unsigned int resv9[1];
 116        unsigned int idlestdpllper;     /* offset 0x70 */
 117        unsigned int resv10[2];
 118        unsigned int clkdcoldodpllper;  /* offset 0x7c */
 119        unsigned int divm4dpllcore;     /* offset 0x80 */
 120        unsigned int divm5dpllcore;     /* offset 0x84 */
 121        unsigned int clkmoddpllmpu;     /* offset 0x88 */
 122        unsigned int clkmoddpllper;     /* offset 0x8c */
 123        unsigned int clkmoddpllcore;    /* offset 0x90 */
 124        unsigned int clkmoddpllddr;     /* offset 0x94 */
 125        unsigned int clkmoddplldisp;    /* offset 0x98 */
 126        unsigned int clkseldpllper;     /* offset 0x9c */
 127        unsigned int divm2dpllddr;      /* offset 0xA0 */
 128        unsigned int divm2dplldisp;     /* offset 0xA4 */
 129        unsigned int divm2dpllmpu;      /* offset 0xA8 */
 130        unsigned int divm2dpllper;      /* offset 0xAC */
 131        unsigned int resv11[1];
 132        unsigned int wkup_uart0ctrl;    /* offset 0xB4 */
 133        unsigned int wkup_i2c0ctrl;     /* offset 0xB8 */
 134        unsigned int wkup_adctscctrl;   /* offset 0xBC */
 135        unsigned int resv12;
 136        unsigned int timer1clkctrl;     /* offset 0xC4 */
 137        unsigned int resv13[4];
 138        unsigned int divm6dpllcore;     /* offset 0xD8 */
 139};
 140
 141/**
 142 * Encapsulating peripheral functional clocks
 143 * pll registers
 144 */
 145struct cm_perpll {
 146        unsigned int l4lsclkstctrl;     /* offset 0x00 */
 147        unsigned int l3sclkstctrl;      /* offset 0x04 */
 148        unsigned int l4fwclkstctrl;     /* offset 0x08 */
 149        unsigned int l3clkstctrl;       /* offset 0x0c */
 150        unsigned int resv1;
 151        unsigned int cpgmac0clkctrl;    /* offset 0x14 */
 152        unsigned int lcdclkctrl;        /* offset 0x18 */
 153        unsigned int usb0clkctrl;       /* offset 0x1C */
 154        unsigned int resv2;
 155        unsigned int tptc0clkctrl;      /* offset 0x24 */
 156        unsigned int emifclkctrl;       /* offset 0x28 */
 157        unsigned int ocmcramclkctrl;    /* offset 0x2c */
 158        unsigned int gpmcclkctrl;       /* offset 0x30 */
 159        unsigned int mcasp0clkctrl;     /* offset 0x34 */
 160        unsigned int uart5clkctrl;      /* offset 0x38 */
 161        unsigned int mmc0clkctrl;       /* offset 0x3C */
 162        unsigned int elmclkctrl;        /* offset 0x40 */
 163        unsigned int i2c2clkctrl;       /* offset 0x44 */
 164        unsigned int i2c1clkctrl;       /* offset 0x48 */
 165        unsigned int spi0clkctrl;       /* offset 0x4C */
 166        unsigned int spi1clkctrl;       /* offset 0x50 */
 167        unsigned int resv3[3];
 168        unsigned int l4lsclkctrl;       /* offset 0x60 */
 169        unsigned int l4fwclkctrl;       /* offset 0x64 */
 170        unsigned int mcasp1clkctrl;     /* offset 0x68 */
 171        unsigned int uart1clkctrl;      /* offset 0x6C */
 172        unsigned int uart2clkctrl;      /* offset 0x70 */
 173        unsigned int uart3clkctrl;      /* offset 0x74 */
 174        unsigned int uart4clkctrl;      /* offset 0x78 */
 175        unsigned int timer7clkctrl;     /* offset 0x7C */
 176        unsigned int timer2clkctrl;     /* offset 0x80 */
 177        unsigned int timer3clkctrl;     /* offset 0x84 */
 178        unsigned int timer4clkctrl;     /* offset 0x88 */
 179        unsigned int resv4[8];
 180        unsigned int gpio1clkctrl;      /* offset 0xAC */
 181        unsigned int gpio2clkctrl;      /* offset 0xB0 */
 182        unsigned int gpio3clkctrl;      /* offset 0xB4 */
 183        unsigned int resv5;
 184        unsigned int tpccclkctrl;       /* offset 0xBC */
 185        unsigned int dcan0clkctrl;      /* offset 0xC0 */
 186        unsigned int dcan1clkctrl;      /* offset 0xC4 */
 187        unsigned int resv6;
 188        unsigned int epwmss1clkctrl;    /* offset 0xCC */
 189        unsigned int emiffwclkctrl;     /* offset 0xD0 */
 190        unsigned int epwmss0clkctrl;    /* offset 0xD4 */
 191        unsigned int epwmss2clkctrl;    /* offset 0xD8 */
 192        unsigned int l3instrclkctrl;    /* offset 0xDC */
 193        unsigned int l3clkctrl;         /* Offset 0xE0 */
 194        unsigned int resv8[2];
 195        unsigned int timer5clkctrl;     /* offset 0xEC */
 196        unsigned int timer6clkctrl;     /* offset 0xF0 */
 197        unsigned int mmc1clkctrl;       /* offset 0xF4 */
 198        unsigned int mmc2clkctrl;       /* offset 0xF8 */
 199        unsigned int resv9[8];
 200        unsigned int l4hsclkstctrl;     /* offset 0x11C */
 201        unsigned int l4hsclkctrl;       /* offset 0x120 */
 202        unsigned int resv10[8];
 203        unsigned int cpswclkstctrl;     /* offset 0x144 */
 204        unsigned int lcdcclkstctrl;     /* offset 0x148 */
 205};
 206
 207/* Encapsulating Display pll registers */
 208struct cm_dpll {
 209        unsigned int resv1;
 210        unsigned int clktimer7clk;      /* offset 0x04 */
 211        unsigned int clktimer2clk;      /* offset 0x08 */
 212        unsigned int clktimer3clk;      /* offset 0x0C */
 213        unsigned int clktimer4clk;      /* offset 0x10 */
 214        unsigned int resv2;
 215        unsigned int clktimer5clk;      /* offset 0x18 */
 216        unsigned int clktimer6clk;      /* offset 0x1C */
 217        unsigned int resv3[2];
 218        unsigned int clktimer1clk;      /* offset 0x28 */
 219        unsigned int resv4[2];
 220        unsigned int clklcdcpixelclk;   /* offset 0x34 */
 221};
 222
 223struct prm_device_inst {
 224        unsigned int prm_rstctrl;
 225        unsigned int prm_rsttime;
 226        unsigned int prm_rstst;
 227};
 228#else
 229/* Encapsulating core pll registers */
 230struct cm_wkuppll {
 231        unsigned int resv0[136];
 232        unsigned int wkl4wkclkctrl;     /* offset 0x220 */
 233        unsigned int resv1[7];
 234        unsigned int usbphy0clkctrl;    /* offset 0x240 */
 235        unsigned int resv112;
 236        unsigned int usbphy1clkctrl;    /* offset 0x248 */
 237        unsigned int resv113[45];
 238        unsigned int wkclkstctrl;       /* offset 0x300 */
 239        unsigned int resv2[15];
 240        unsigned int wkup_i2c0ctrl;     /* offset 0x340 */
 241        unsigned int resv3;
 242        unsigned int wkup_uart0ctrl;    /* offset 0x348 */
 243        unsigned int resv4[5];
 244        unsigned int wkctrlclkctrl;     /* offset 0x360 */
 245        unsigned int resv5;
 246        unsigned int wkgpio0clkctrl;    /* offset 0x368 */
 247
 248        unsigned int resv6[109];
 249        unsigned int clkmoddpllcore;    /* offset 0x520 */
 250        unsigned int idlestdpllcore;    /* offset 0x524 */
 251        unsigned int resv61;
 252        unsigned int clkseldpllcore;    /* offset 0x52C */
 253        unsigned int resv7[2];
 254        unsigned int divm4dpllcore;     /* offset 0x538 */
 255        unsigned int divm5dpllcore;     /* offset 0x53C */
 256        unsigned int divm6dpllcore;     /* offset 0x540 */
 257
 258        unsigned int resv8[7];
 259        unsigned int clkmoddpllmpu;     /* offset 0x560 */
 260        unsigned int idlestdpllmpu;     /* offset 0x564 */
 261        unsigned int resv9;
 262        unsigned int clkseldpllmpu;     /* offset 0x56c */
 263        unsigned int divm2dpllmpu;      /* offset 0x570 */
 264
 265        unsigned int resv10[11];
 266        unsigned int clkmoddpllddr;     /* offset 0x5A0 */
 267        unsigned int idlestdpllddr;     /* offset 0x5A4 */
 268        unsigned int resv11;
 269        unsigned int clkseldpllddr;     /* offset 0x5AC */
 270        unsigned int divm2dpllddr;      /* offset 0x5B0 */
 271
 272        unsigned int resv12[11];
 273        unsigned int clkmoddpllper;     /* offset 0x5E0 */
 274        unsigned int idlestdpllper;     /* offset 0x5E4 */
 275        unsigned int resv13;
 276        unsigned int clkseldpllper;     /* offset 0x5EC */
 277        unsigned int divm2dpllper;      /* offset 0x5F0 */
 278        unsigned int resv14[8];
 279        unsigned int clkdcoldodpllper;  /* offset 0x614 */
 280
 281        unsigned int resv15[2];
 282        unsigned int clkmoddplldisp;    /* offset 0x620 */
 283        unsigned int resv16[2];
 284        unsigned int clkseldplldisp;    /* offset 0x62C */
 285        unsigned int divm2dplldisp;     /* offset 0x630 */
 286};
 287
 288/*
 289 * Encapsulating peripheral functional clocks
 290 * pll registers
 291 */
 292struct cm_perpll {
 293        unsigned int l3clkstctrl;       /* offset 0x00 */
 294        unsigned int resv0[7];
 295        unsigned int l3clkctrl;         /* Offset 0x20 */
 296        unsigned int resv112[7];
 297        unsigned int l3instrclkctrl;    /* offset 0x40 */
 298        unsigned int resv2[3];
 299        unsigned int ocmcramclkctrl;    /* offset 0x50 */
 300        unsigned int resv3[9];
 301        unsigned int tpccclkctrl;       /* offset 0x78 */
 302        unsigned int resv4;
 303        unsigned int tptc0clkctrl;      /* offset 0x80 */
 304
 305        unsigned int resv5[7];
 306        unsigned int l4hsclkctrl;       /* offset 0x0A0 */
 307        unsigned int resv6;
 308        unsigned int l4fwclkctrl;       /* offset 0x0A8 */
 309        unsigned int resv7[85];
 310        unsigned int l3sclkstctrl;      /* offset 0x200 */
 311        unsigned int resv8[7];
 312        unsigned int gpmcclkctrl;       /* offset 0x220 */
 313        unsigned int resv9[5];
 314        unsigned int mcasp0clkctrl;     /* offset 0x238 */
 315        unsigned int resv10;
 316        unsigned int mcasp1clkctrl;     /* offset 0x240 */
 317        unsigned int resv11;
 318        unsigned int mmc2clkctrl;       /* offset 0x248 */
 319        unsigned int resv12[3];
 320        unsigned int qspiclkctrl;       /* offset 0x258 */
 321        unsigned int resv121;
 322        unsigned int usb0clkctrl;       /* offset 0x260 */
 323        unsigned int resv122;
 324        unsigned int usb1clkctrl;       /* offset 0x268 */
 325        unsigned int resv13[101];
 326        unsigned int l4lsclkstctrl;     /* offset 0x400 */
 327        unsigned int resv14[7];
 328        unsigned int l4lsclkctrl;       /* offset 0x420 */
 329        unsigned int resv15;
 330        unsigned int dcan0clkctrl;      /* offset 0x428 */
 331        unsigned int resv16;
 332        unsigned int dcan1clkctrl;      /* offset 0x430 */
 333        unsigned int resv17[13];
 334        unsigned int elmclkctrl;        /* offset 0x468 */
 335
 336        unsigned int resv18[3];
 337        unsigned int gpio1clkctrl;      /* offset 0x478 */
 338        unsigned int resv19;
 339        unsigned int gpio2clkctrl;      /* offset 0x480 */
 340        unsigned int resv20;
 341        unsigned int gpio3clkctrl;      /* offset 0x488 */
 342        unsigned int resv41;
 343        unsigned int gpio4clkctrl;      /* offset 0x490 */
 344        unsigned int resv42;
 345        unsigned int gpio5clkctrl;      /* offset 0x498 */
 346        unsigned int resv21[3];
 347
 348        unsigned int i2c1clkctrl;       /* offset 0x4A8 */
 349        unsigned int resv22;
 350        unsigned int i2c2clkctrl;       /* offset 0x4B0 */
 351        unsigned int resv23[3];
 352        unsigned int mmc0clkctrl;       /* offset 0x4C0 */
 353        unsigned int resv24;
 354        unsigned int mmc1clkctrl;       /* offset 0x4C8 */
 355
 356        unsigned int resv25[13];
 357        unsigned int spi0clkctrl;       /* offset 0x500 */
 358        unsigned int resv26;
 359        unsigned int spi1clkctrl;       /* offset 0x508 */
 360        unsigned int resv27[9];
 361        unsigned int timer2clkctrl;     /* offset 0x530 */
 362        unsigned int resv28;
 363        unsigned int timer3clkctrl;     /* offset 0x538 */
 364        unsigned int resv29;
 365        unsigned int timer4clkctrl;     /* offset 0x540 */
 366        unsigned int resv30[5];
 367        unsigned int timer7clkctrl;     /* offset 0x558 */
 368
 369        unsigned int resv31[9];
 370        unsigned int uart1clkctrl;      /* offset 0x580 */
 371        unsigned int resv32;
 372        unsigned int uart2clkctrl;      /* offset 0x588 */
 373        unsigned int resv33;
 374        unsigned int uart3clkctrl;      /* offset 0x590 */
 375        unsigned int resv34;
 376        unsigned int uart4clkctrl;      /* offset 0x598 */
 377        unsigned int resv35;
 378        unsigned int uart5clkctrl;      /* offset 0x5A0 */
 379        unsigned int resv36[5];
 380        unsigned int usbphyocp2scp0clkctrl;     /* offset 0x5B8 */
 381        unsigned int resv361;
 382        unsigned int usbphyocp2scp1clkctrl;     /* offset 0x5C0 */
 383        unsigned int resv3611[79];
 384
 385        unsigned int emifclkstctrl;     /* offset 0x700 */
 386        unsigned int resv362[7];
 387        unsigned int emifclkctrl;       /* offset 0x720 */
 388        unsigned int resv37[3];
 389        unsigned int emiffwclkctrl;     /* offset 0x730 */
 390        unsigned int resv371;
 391        unsigned int otfaemifclkctrl;   /* offset 0x738 */
 392        unsigned int resv38[57];
 393        unsigned int lcdclkctrl;        /* offset 0x820 */
 394        unsigned int resv39[183];
 395        unsigned int cpswclkstctrl;     /* offset 0xB00 */
 396        unsigned int resv40[7];
 397        unsigned int cpgmac0clkctrl;    /* offset 0xB20 */
 398};
 399
 400struct cm_device_inst {
 401        unsigned int cm_clkout1_ctrl;
 402        unsigned int cm_dll_ctrl;
 403};
 404
 405struct prm_device_inst {
 406        unsigned int prm_rstctrl;
 407        unsigned int prm_rstst;
 408};
 409
 410struct cm_dpll {
 411        unsigned int resv1;
 412        unsigned int clktimer2clk;      /* offset 0x04 */
 413        unsigned int resv2[11];
 414        unsigned int clkselmacclk;      /* offset 0x34 */ 
 415};
 416#endif /* CONFIG_AM43XX */
 417
 418/* Control Module RTC registers */
 419struct cm_rtc {
 420        unsigned int rtcclkctrl;        /* offset 0x0 */
 421        unsigned int clkstctrl;         /* offset 0x4 */
 422};
 423
 424/* Watchdog timer registers */
 425struct wd_timer {
 426        unsigned int resv1[4];
 427        unsigned int wdtwdsc;   /* offset 0x010 */
 428        unsigned int wdtwdst;   /* offset 0x014 */
 429        unsigned int wdtwisr;   /* offset 0x018 */
 430        unsigned int wdtwier;   /* offset 0x01C */
 431        unsigned int wdtwwer;   /* offset 0x020 */
 432        unsigned int wdtwclr;   /* offset 0x024 */
 433        unsigned int wdtwcrr;   /* offset 0x028 */
 434        unsigned int wdtwldr;   /* offset 0x02C */
 435        unsigned int wdtwtgr;   /* offset 0x030 */
 436        unsigned int wdtwwps;   /* offset 0x034 */
 437        unsigned int resv2[3];
 438        unsigned int wdtwdly;   /* offset 0x044 */
 439        unsigned int wdtwspr;   /* offset 0x048 */
 440        unsigned int resv3[1];
 441        unsigned int wdtwqeoi;  /* offset 0x050 */
 442        unsigned int wdtwqstar; /* offset 0x054 */
 443        unsigned int wdtwqsta;  /* offset 0x058 */
 444        unsigned int wdtwqens;  /* offset 0x05C */
 445        unsigned int wdtwqenc;  /* offset 0x060 */
 446        unsigned int resv4[39];
 447        unsigned int wdt_unfr;  /* offset 0x100 */
 448};
 449
 450/* Timer 32 bit registers */
 451struct gptimer {
 452        unsigned int tidr;              /* offset 0x00 */
 453        unsigned char res1[12];
 454        unsigned int tiocp_cfg;         /* offset 0x10 */
 455        unsigned char res2[12];
 456        unsigned int tier;              /* offset 0x20 */
 457        unsigned int tistatr;           /* offset 0x24 */
 458        unsigned int tistat;            /* offset 0x28 */
 459        unsigned int tisr;              /* offset 0x2c */
 460        unsigned int tcicr;             /* offset 0x30 */
 461        unsigned int twer;              /* offset 0x34 */
 462        unsigned int tclr;              /* offset 0x38 */
 463        unsigned int tcrr;              /* offset 0x3c */
 464        unsigned int tldr;              /* offset 0x40 */
 465        unsigned int ttgr;              /* offset 0x44 */
 466        unsigned int twpc;              /* offset 0x48 */
 467        unsigned int tmar;              /* offset 0x4c */
 468        unsigned int tcar1;             /* offset 0x50 */
 469        unsigned int tscir;             /* offset 0x54 */
 470        unsigned int tcar2;             /* offset 0x58 */
 471};
 472
 473/* UART Registers */
 474struct uart_sys {
 475        unsigned int resv1[21];
 476        unsigned int uartsyscfg;        /* offset 0x54 */
 477        unsigned int uartsyssts;        /* offset 0x58 */
 478};
 479
 480/* VTP Registers */
 481struct vtp_reg {
 482        unsigned int vtp0ctrlreg;
 483};
 484
 485/* Control Status Register */
 486struct ctrl_stat {
 487        unsigned int resv1[16];
 488        unsigned int statusreg;         /* ofset 0x40 */
 489        unsigned int resv2[51];
 490        unsigned int secure_emif_sdram_config;  /* offset 0x0110 */
 491        unsigned int resv3[319];
 492        unsigned int dev_attr;
 493};
 494
 495/* AM33XX GPIO registers */
 496#define OMAP_GPIO_REVISION              0x0000
 497#define OMAP_GPIO_SYSCONFIG             0x0010
 498#define OMAP_GPIO_SYSSTATUS             0x0114
 499#define OMAP_GPIO_IRQSTATUS1            0x002c
 500#define OMAP_GPIO_IRQSTATUS2            0x0030
 501#define OMAP_GPIO_IRQSTATUS_SET_0       0x0034
 502#define OMAP_GPIO_IRQSTATUS_SET_1       0x0038
 503#define OMAP_GPIO_CTRL                  0x0130
 504#define OMAP_GPIO_OE                    0x0134
 505#define OMAP_GPIO_DATAIN                0x0138
 506#define OMAP_GPIO_DATAOUT               0x013c
 507#define OMAP_GPIO_LEVELDETECT0          0x0140
 508#define OMAP_GPIO_LEVELDETECT1          0x0144
 509#define OMAP_GPIO_RISINGDETECT          0x0148
 510#define OMAP_GPIO_FALLINGDETECT         0x014c
 511#define OMAP_GPIO_DEBOUNCE_EN           0x0150
 512#define OMAP_GPIO_DEBOUNCE_VAL          0x0154
 513#define OMAP_GPIO_CLEARDATAOUT          0x0190
 514#define OMAP_GPIO_SETDATAOUT            0x0194
 515
 516/* Control Device Register */
 517
 518 /* Control Device Register */
 519#define MREQPRIO_0_SAB_INIT1_MASK       0xFFFFFF8F
 520#define MREQPRIO_0_SAB_INIT0_MASK       0xFFFFFFF8
 521#define MREQPRIO_1_DSS_MASK             0xFFFFFF8F
 522
 523struct ctrl_dev {
 524        unsigned int deviceid;          /* offset 0x00 */
 525        unsigned int resv1[7];
 526        unsigned int usb_ctrl0;         /* offset 0x20 */
 527        unsigned int resv2;
 528        unsigned int usb_ctrl1;         /* offset 0x28 */
 529        unsigned int resv3;
 530        unsigned int macid0l;           /* offset 0x30 */
 531        unsigned int macid0h;           /* offset 0x34 */
 532        unsigned int macid1l;           /* offset 0x38 */
 533        unsigned int macid1h;           /* offset 0x3c */
 534        unsigned int resv4[4];
 535        unsigned int miisel;            /* offset 0x50 */
 536        unsigned int resv5[7];
 537        unsigned int mreqprio_0;        /* offset 0x70 */
 538        unsigned int mreqprio_1;        /* offset 0x74 */
 539        unsigned int resv6[97];
 540        unsigned int efuse_sma;         /* offset 0x1FC */
 541};
 542
 543/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
 544#define BW_LIMITER_BW_FRAC_MASK         0xFFFFFFE0
 545#define BW_LIMITER_BW_INT_MASK          0xFFFFFFF0
 546#define BW_LIMITER_BW_WATERMARK_MASK    0xFFFFF800
 547
 548struct l3f_cfg_bwlimiter {
 549        u32 padding0[2];
 550        u32 modena_init0_bw_fractional;
 551        u32 modena_init0_bw_integer;
 552        u32 modena_init0_watermark_0;
 553};
 554
 555/* gmii_sel register defines */
 556#define GMII1_SEL_MII           0x0
 557#define GMII1_SEL_RMII          0x1
 558#define GMII1_SEL_RGMII         0x2
 559#define GMII2_SEL_MII           0x0
 560#define GMII2_SEL_RMII          0x4
 561#define GMII2_SEL_RGMII         0x8
 562#define RGMII1_IDMODE           BIT(4)
 563#define RGMII2_IDMODE           BIT(5)
 564#define RMII1_IO_CLK_EN         BIT(6)
 565#define RMII2_IO_CLK_EN         BIT(7)
 566
 567#define MII_MODE_ENABLE         (GMII1_SEL_MII | GMII2_SEL_MII)
 568#define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
 569#define RGMII_MODE_ENABLE       (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
 570#define RGMII_INT_DELAY         (RGMII1_IDMODE | RGMII2_IDMODE)
 571#define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
 572
 573/* PWMSS */
 574struct pwmss_regs {
 575        unsigned int idver;
 576        unsigned int sysconfig;
 577        unsigned int clkconfig;
 578        unsigned int clkstatus;
 579};
 580#define ECAP_CLK_EN             BIT(0)
 581#define ECAP_CLK_STOP_REQ       BIT(1)
 582
 583struct pwmss_ecap_regs {
 584        unsigned int tsctr;
 585        unsigned int ctrphs;
 586        unsigned int cap1;
 587        unsigned int cap2;
 588        unsigned int cap3;
 589        unsigned int cap4;
 590        unsigned int resv1[4];
 591        unsigned short ecctl1;
 592        unsigned short ecctl2;
 593};
 594
 595/* Capture Control register 2 */
 596#define ECTRL2_SYNCOSEL_MASK    (0x03 << 6)
 597#define ECTRL2_MDSL_ECAP        BIT(9)
 598#define ECTRL2_CTRSTP_FREERUN   BIT(4)
 599#define ECTRL2_PLSL_LOW         BIT(10)
 600#define ECTRL2_SYNC_EN          BIT(5)
 601
 602#endif /* __ASSEMBLY__ */
 603#endif /* __KERNEL_STRICT_NAMES */
 604
 605#endif /* _AM33XX_CPU_H */
 606