LXR uboot/arch/arm/include/asm/arch-rockchip/clock.h

   1/*
   2 * (C) Copyright 2015 Google, Inc
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0
   5 */
   6
   7#ifndef _ASM_ARCH_CLOCK_H
   8#define _ASM_ARCH_CLOCK_H
   9
  10/* define pll mode */
  11#define RKCLK_PLL_MODE_SLOW             0
  12#define RKCLK_PLL_MODE_NORMAL           1
  13
  14enum {
  15        ROCKCHIP_SYSCON_NOC,
  16        ROCKCHIP_SYSCON_GRF,
  17        ROCKCHIP_SYSCON_SGRF,
  18        ROCKCHIP_SYSCON_PMU,
  19};
  20
  21/* Standard Rockchip clock numbers */
  22enum rk_clk_id {
  23        CLK_OSC,
  24        CLK_ARM,
  25        CLK_DDR,
  26        CLK_CODEC,
  27        CLK_GENERAL,
  28        CLK_NEW,
  29
  30        CLK_COUNT,
  31};
  32
  33static inline int rk_pll_id(enum rk_clk_id clk_id)
  34{
  35        return clk_id - 1;
  36}
  37
  38/**
  39 * clk_get_divisor() - Calculate the required clock divisior
  40 *
  41 * Given an input rate and a required output_rate, calculate the Rockchip
  42 * divisor needed to achieve this.
  43 *
  44 * @input_rate:         Input clock rate in Hz
  45 * @output_rate:        Output clock rate in Hz
  46 * @return divisor register value to use
  47 */
  48static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
  49{
  50        uint clk_div;
  51
  52        clk_div = input_rate / output_rate;
  53        clk_div = (clk_div + 1) & 0xfffe;
  54
  55        return clk_div;
  56}
  57
  58/**
  59 * rockchip_get_cru() - get a pointer to the clock/reset unit registers
  60 *
  61 * @return pointer to registers, or -ve error on error
  62 */
  63void *rockchip_get_cru(void);
  64
  65struct rk3288_cru;
  66struct rk3288_grf;
  67
  68void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
  69
  70int rockchip_get_clk(struct udevice **devp);
  71
  72#endif
  73