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11#include <common.h>
12#include <errno.h>
13#include <spl.h>
14#include <asm/arch/cpu.h>
15#include <asm/arch/hardware.h>
16#include <asm/arch/omap.h>
17#include <asm/arch/ddr_defs.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/gpio.h>
20#include <asm/arch/mmc_host_def.h>
21#include <asm/arch/sys_proto.h>
22#include <asm/arch/mem.h>
23#include <asm/io.h>
24#include <asm/emif.h>
25#include <asm/gpio.h>
26#include <i2c.h>
27#include <miiphy.h>
28#include <cpsw.h>
29#include <power/tps65217.h>
30#include <power/tps65910.h>
31#include <environment.h>
32#include <watchdog.h>
33#include <environment.h>
34#include "board.h"
35
36DECLARE_GLOBAL_DATA_PTR;
37
38
39#define GPIO_DDR_VTT_EN 7
40
41static __maybe_unused struct ctrl_dev *cdev =
42 (struct ctrl_dev *)CTRL_DEVICE_BASE;
43
44
45
46
47
48
49static int read_eeprom(struct board_eeconfig *header)
50{
51
52 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
53 return -ENODEV;
54
55
56 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
57 sizeof(struct board_eeconfig)))
58 return -EIO;
59
60 if (header->magic != BOARD_MAGIC) {
61
62 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
63 sizeof(struct board_eeconfig)))
64 return -EIO;
65
66 if (header->magic != BOARD_MAGIC)
67 return -EINVAL;
68 }
69 return 0;
70}
71
72
73
74
75enum board_type get_board_type(bool debug)
76{
77 int ecode;
78 struct board_eeconfig header;
79
80 ecode = read_eeprom(&header);
81 if (ecode == 0) {
82 if (header.version[1] == 'A') {
83 if (debug)
84 puts("=== Detected Board model BAV335x Rev.A");
85 return BAV335A;
86 } else if (header.version[1] == 'B') {
87 if (debug)
88 puts("=== Detected Board model BAV335x Rev.B");
89 return BAV335B;
90 } else if (debug) {
91 puts("### Un-known board model in serial-EE\n");
92 }
93 } else if (debug) {
94 switch (ecode) {
95 case -ENODEV:
96 puts("### Board doesn't have a serial-EE\n");
97 break;
98 case -EINVAL:
99 puts("### Board serial-EE signature is incorrect.\n");
100 break;
101 default:
102 puts("### IO Error reading serial-EE.\n");
103 break;
104 }
105 }
106
107#if (CONFIG_BAV_VERSION == 1)
108 if (debug)
109 puts("### Selecting BAV335A as per config\n");
110 return BAV335A;
111#elif (CONFIG_BAV_VERSION == 2)
112 if (debug)
113 puts("### Selecting BAV335B as per config\n");
114 return BAV335B;
115#endif
116#if (NOT_DEFINED == 2)
117#error "SHOULD NEVER DISPLAY THIS"
118#endif
119
120 if (debug)
121 puts("### Defaulting to model BAV335x Rev.B\n");
122 return BAV335B;
123}
124
125
126
127#ifndef CONFIG_SKIP_LOWLEVEL_INIT
128static const struct ddr_data ddr3_bav335x_data = {
129 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
130 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
131 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
132 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
133};
134
135static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
136 .cmd0csratio = MT41K256M16HA125E_RATIO,
137 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
138 .cmd1csratio = MT41K256M16HA125E_RATIO,
139 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
140 .cmd2csratio = MT41K256M16HA125E_RATIO,
141 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
142};
143
144
145static struct emif_regs ddr3_bav335x_emif_reg_data = {
146 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
147 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
148 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
149 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
150 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
151 .zq_config = MT41K256M16HA125E_ZQ_CFG,
152 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
153};
154
155
156#ifdef CONFIG_SPL_OS_BOOT
157int spl_start_uboot(void)
158{
159
160 if (serial_tstc() && serial_getc() == 'c')
161 return 1;
162
163#ifdef CONFIG_SPL_ENV_SUPPORT
164 env_init();
165 env_relocate_spec();
166 if (getenv_yesno("boot_os") != 1)
167 return 1;
168#endif
169
170 return 0;
171}
172#endif
173
174#define OSC (V_OSCK/1000000)
175const struct dpll_params dpll_ddr = {
176 266, OSC-1, 1, -1, -1, -1, -1};
177const struct dpll_params dpll_ddr_evm_sk = {
178 303, OSC-1, 1, -1, -1, -1, -1};
179const struct dpll_params dpll_ddr_bone_black = {
180 400, OSC-1, 1, -1, -1, -1, -1};
181
182void am33xx_spl_board_init(void)
183{
184
185 (void)get_board_type(true);
186
187
188
189 dpll_mpu_opp100.m = MPUPLL_M_1000;
190
191 if (i2c_probe(TPS65217_CHIP_PM))
192 return;
193
194
195 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
196 TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
197 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
198 puts("! tps65217_reg_write: could not set USB limit\n");
199
200
201 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
202 TPS65217_DCDC_VOLT_SEL_1125MV)) {
203 puts("! tps65217_reg_write: could not set Core Voltage\n");
204 return;
205 }
206
207
208 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
209
210
211 if (tps65217_voltage_update(TPS65217_DEFDCDC2,
212 TPS65217_DCDC_VOLT_SEL_1325MV)) {
213 puts("! tps65217_reg_write: could not set MPU Voltage\n");
214 return;
215 }
216
217
218
219
220
221 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
222 TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
223 puts("! tps65217_reg_write: could not set LDO3\n");
224
225 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
226 TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
227 puts("! tps65217_reg_write: could not set LDO4\n");
228
229
230 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
231}
232
233const struct dpll_params *get_dpll_ddr_params(void)
234{
235 enable_i2c0_pin_mux();
236 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
237
238 return &dpll_ddr_bone_black;
239}
240
241void set_uart_mux_conf(void)
242{
243#if CONFIG_CONS_INDEX == 1
244 enable_uart0_pin_mux();
245#elif CONFIG_CONS_INDEX == 2
246 enable_uart1_pin_mux();
247#elif CONFIG_CONS_INDEX == 3
248 enable_uart2_pin_mux();
249#elif CONFIG_CONS_INDEX == 4
250 enable_uart3_pin_mux();
251#elif CONFIG_CONS_INDEX == 5
252 enable_uart4_pin_mux();
253#elif CONFIG_CONS_INDEX == 6
254 enable_uart5_pin_mux();
255#endif
256}
257
258void set_mux_conf_regs(void)
259{
260 enum board_type board;
261
262 board = get_board_type(false);
263 enable_board_pin_mux(board);
264}
265
266const struct ctrl_ioregs ioregs_bonelt = {
267 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
268 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
269 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
270 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
271 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
272};
273
274
275void sdram_init(void)
276{
277 config_ddr(400, &ioregs_bonelt,
278 &ddr3_bav335x_data,
279 &ddr3_bav335x_cmd_ctrl_data,
280 &ddr3_bav335x_emif_reg_data, 0);
281}
282#endif
283
284
285
286
287int board_init(void)
288{
289#if defined(CONFIG_HW_WATCHDOG)
290 hw_watchdog_init();
291#endif
292
293 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
294#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
295 gpmc_init();
296#endif
297 return 0;
298}
299
300#ifdef CONFIG_BOARD_LATE_INIT
301int board_late_init(void)
302{
303#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
304 setenv("board_name", "BAV335xB");
305 setenv("board_rev", "B");
306#endif
307 return 0;
308}
309#endif
310
311
312#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
313 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
314static void cpsw_control(int enabled)
315{
316
317 return;
318}
319
320static struct cpsw_slave_data cpsw_slaves[] = {
321 {
322 .slave_reg_ofs = 0x208,
323 .sliver_reg_ofs = 0xd80,
324 .phy_addr = 0,
325 },
326 {
327 .slave_reg_ofs = 0x308,
328 .sliver_reg_ofs = 0xdc0,
329 .phy_addr = 1,
330 },
331};
332
333static struct cpsw_platform_data cpsw_data = {
334 .mdio_base = CPSW_MDIO_BASE,
335 .cpsw_base = CPSW_BASE,
336 .mdio_div = 0xff,
337 .channels = 8,
338 .cpdma_reg_ofs = 0x800,
339 .slaves = 1,
340 .slave_data = cpsw_slaves,
341 .ale_reg_ofs = 0xd00,
342 .ale_entries = 1024,
343 .host_port_reg_ofs = 0x108,
344 .hw_stats_reg_ofs = 0x900,
345 .bd_ram_ofs = 0x2000,
346 .mac_control = (1 << 5),
347 .control = cpsw_control,
348 .host_port_num = 0,
349 .version = CPSW_CTRL_VERSION_2,
350};
351#endif
352
353
354
355
356
357
358
359
360
361
362
363#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
364 defined(CONFIG_SPL_BUILD)) || \
365 ((defined(CONFIG_DRIVER_TI_CPSW) || \
366 defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
367 !defined(CONFIG_SPL_BUILD))
368int board_eth_init(bd_t *bis)
369{
370 int ecode, rv, n;
371 uint8_t mac_addr[6];
372 struct board_eeconfig header;
373 __maybe_unused enum board_type board;
374
375
376 n = 0;
377 mac_addr[0] = 0;
378 mac_addr[1] = 0x20;
379 mac_addr[2] = 0x18;
380 mac_addr[3] = 0x1C;
381 mac_addr[4] = 0x00;
382 mac_addr[5] = 0x01;
383
384 ecode = read_eeprom(&header);
385
386 if ((ecode == 0) &&
387 is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
388 memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
389 }
390
391
392#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
393 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
394
395 if (!getenv("ethaddr")) {
396 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
397
398 if (is_valid_ethaddr(mac_addr))
399 eth_setenv_enetaddr("ethaddr", mac_addr);
400 }
401
402#ifdef CONFIG_DRIVER_TI_CPSW
403
404 board = get_board_type(false);
405
406
407 if (board == BAV335A) {
408 writel(MII_MODE_ENABLE, &cdev->miisel);
409 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
410 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
411 }
412
413 else {
414 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
415 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
416 = PHY_INTERFACE_MODE_RGMII;
417 }
418
419 rv = cpsw_register(&cpsw_data);
420 if (rv < 0)
421 printf("Error %d registering CPSW switch\n", rv);
422 else
423 n += rv;
424#endif
425
426#endif
427
428 return n;
429}
430#endif
431
