LXR uboot/board/micronas/vct/dcgu.h

   1/*
   2 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
   3 *
   4 * Copyright (C) 2006 Micronas GmbH
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#ifndef _DCGU_H
  10#define _DCGU_H
  11
  12enum dcgu_switch {
  13        DCGU_SWITCH_OFF,        /* Switch off                           */
  14        DCGU_SWITCH_ON          /* Switch on                            */
  15};
  16
  17enum dcgu_hw_module {
  18        DCGU_HW_MODULE_DCGU,    /* Selects digital clock gen. unit      */
  19
  20        DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface        */
  21        DCGU_HW_MODULE_SCI,     /* Selects SCI target agent port modules*/
  22
  23        DCGU_HW_MODULE_MR1,     /* Selects first MPEG reader module     */
  24        DCGU_HW_MODULE_MR2,     /* Selects second MPEG reader module    */
  25        DCGU_HW_MODULE_MVD,     /* Selects MPEG video decoder module    */
  26        DCGU_HW_MODULE_DVP,     /* Selects dig video processing module  */
  27        DCGU_HW_MODULE_CVE,     /* Selects color video encoder module   */
  28        DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module         */
  29
  30        DCGU_HW_MODULE_SSI_S,   /* Selects slave sync serial interface  */
  31        DCGU_HW_MODULE_SSI_M,   /* Selects master sync serial interface */
  32
  33        DCGU_HW_MODULE_GA,      /* Selects graphics accelerator module  */
  34        DCGU_HW_MODULE_DGPU,    /* Selects digital graphics processing  */
  35
  36        DCGU_HW_MODULE_UART_1,  /* Selects first UART module            */
  37        DCGU_HW_MODULE_UART_2,  /* Selects second UART module           */
  38
  39        DCGU_HW_MODULE_AD,      /* Selects audio decoder module         */
  40        DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing    */
  41        DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/
  42        DCGU_HW_MODULE_SPDIF,   /* Selects sony philips digital interf. */
  43
  44        DCGU_HW_MODULE_TSIO,    /* Selects trasnport stream input/output*/
  45        DCGU_HW_MODULE_TSD,     /* Selects trasnport stream decoder     */
  46        DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */
  47
  48        DCGU_HW_MODULE_USBH,    /* Selects USB hub module               */
  49        DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */
  50        DCGU_HW_MODULE_USB_60,  /* Selects USB 60 module                */
  51        DCGU_HW_MODULE_USB_24,  /* Selects USB 24 module                */
  52
  53        DCGU_HW_MODULE_PERI,    /* Selects all mod connected to clkperi20*/
  54        DCGU_HW_MODULE_WDT,     /* Selects wtg timer mod con to clkperi20*/
  55        DCGU_HW_MODULE_I2C1,    /* Selects first I2C mod con to clkperi20*/
  56        DCGU_HW_MODULE_I2C2,    /* Selects 2nd I2C mod con to clkperi20 */
  57        DCGU_HW_MODULE_GPIO1,   /* Selects gpio module 1                */
  58        DCGU_HW_MODULE_GPIO2,   /* Selects gpio module 2                */
  59
  60        DCGU_HW_MODULE_GPT,     /* Selects gpt mod connected to clkperi20*/
  61        DCGU_HW_MODULE_PWM,     /* Selects pwm mod connected to clkperi20*/
  62
  63        DCGU_HW_MODULE_MPC,     /* Selects multi purpose cipher module  */
  64        DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key     */
  65
  66        DCGU_HW_MODULE_COM,     /* Selects COM unit module              */
  67        DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module          */
  68        DCGU_HW_MODULE_FWSRAM,  /* Selects firmware SRAM module         */
  69
  70        DCGU_HW_MODULE_EBI,     /* Selects external bus interface module*/
  71        DCGU_HW_MODULE_I2S,     /* Selects integrated interchip sound   */
  72        DCGU_HW_MODULE_MSMC,    /* Selects memory stick and mmc module  */
  73        DCGU_HW_MODULE_SMC,     /* Selects smartcard interface module   */
  74
  75        DCGU_HW_MODULE_IRQC,    /* Selects interrupt C module           */
  76        DCGU_HW_MODULE_TOP,     /* Selects top level pinmux module      */
  77        DCGU_HW_MODULE_SRAM,    /* Selects SRAM module                  */
  78        DCGU_HW_MODULE_EIC,     /* Selects External Interrupt controller*/
  79        DCGU_HW_MODULE_CPU,     /* Selects CPU subsystem module         */
  80        DCGU_HW_MODULE_SCC,     /* Selects SCC module                   */
  81        DCGU_HW_MODULE_MM,      /* Selects Memory Manager module        */
  82        DCGU_HW_MODULE_BCU,     /* Selects Buffer Configuration Unit    */
  83        DCGU_HW_MODULE_FH,      /* Selects FIFO Handler module          */
  84        DCGU_HW_MODULE_IMU,     /* Selects Interrupt Management Unit    */
  85        DCGU_HW_MODULE_MDU,     /* Selects MCI Debug Unit module        */
  86        DCGU_HW_MODULE_SI2OCP   /* Selects Standard Interface to OCP bridge*/
  87};
  88
  89union dcgu_clk_en1 {
  90        u32 reg;
  91        struct {
  92                u32 res1:8;             /* reserved                     */
  93                u32 en_clkmsmc:1;       /* Enable bit for clkmsmc (#)   */
  94                u32 en_clkssi_s:1;      /* Enable bit for clkssi_s (#)  */
  95                u32 en_clkssi_m:1;      /* Enable bit for clkssi_m (#)  */
  96                u32 en_clksmc:1;        /* Enable bit for clksmc (#)    */
  97                u32 en_clkebi:1;        /* Enable bit for clkebi (#)    */
  98                u32 en_usbpll:1;        /* Enable bit for the USB PLL   */
  99                u32 en_clkusb60:1;      /* Enable bit for clkusb60 (#)  */
 100                u32 en_clkusb24:1;      /* Enable bit for clkusb24 (#)  */
 101                u32 en_clkuart2:1;      /* Enable bit for clkuart2 (#)  */
 102                u32 en_clkuart1:1;      /* Enable bit for clkuart1 (#)  */
 103                u32 en_clkperi20:1;     /* Enable bit for clkperi20 (#) */
 104                u32 res2:3;             /* reserved                     */
 105                u32 en_clk_i2s_dly:1;   /* Enable bit for clk_scc_abp   */
 106                u32 en_clk_scc_abp:1;   /* Enable bit for clk_scc_abp   */
 107                u32 en_clk_dtv_spdo:1;  /* Enable bit for clk_dtv_spdo  */
 108                u32 en_clkad:1;         /* Enable bit for clkad (#)     */
 109                u32 en_clkmvd:1;        /* Enable bit for clkmvd (#)    */
 110                u32 en_clktsd:1;        /* Enable bit for clktsd (#)    */
 111                u32 en_clkga:1;         /* Enable bit for clkga (#)     */
 112                u32 en_clkdvp:1;        /* Enable bit for clkdvp (#)    */
 113                u32 en_clkmr2:1;        /* Enable bit for clkmr2 (#)    */
 114                u32 en_clkmr1:1;        /* Enable bit for clkmr1 (#)    */
 115        } bits;
 116};
 117
 118union dcgu_clk_en2 {
 119        u32 reg;
 120        struct {
 121                u32 res1:31;            /* reserved                     */
 122                u32 en_clkcpu:1;        /* Enable bit for clkcpu        */
 123        } bits;
 124};
 125
 126union dcgu_reset_unit1 {
 127        u32 reg;
 128        struct {
 129                u32 res1:1;
 130                u32 swreset_clkmsmc:1;
 131                u32 swreset_clkssi_s:1;
 132                u32 swreset_clkssi_m:1;
 133                u32 swreset_clksmc:1;
 134                u32 swreset_clkebi:1;
 135                u32 swreset_clkusb60:1;
 136                u32 swreset_clkusb24:1;
 137                u32 swreset_clkuart2:1;
 138                u32 swreset_clkuart1:1;
 139                u32 swreset_pwm:1;
 140                u32 swreset_gpt:1;
 141                u32 swreset_i2c2:1;
 142                u32 swreset_i2c1:1;
 143                u32 swreset_gpio2:1;
 144                u32 swreset_gpio1:1;
 145                u32 swreset_clkcpu:1;
 146                u32 res2:2;
 147                u32 swreset_clk_i2s_dly:1;
 148                u32 swreset_clk_scc_abp:1;
 149                u32 swreset_clk_dtv_spdo:1;
 150                u32 swreset_clkad:1;
 151                u32 swreset_clkmvd:1;
 152                u32 swreset_clktsd:1;
 153                u32 swreset_clktsio:1;
 154                u32 swreset_clkga:1;
 155                u32 swreset_clkmpc:1;
 156                u32 swreset_clkcve:1;
 157                u32 swreset_clkdvp:1;
 158                u32 swreset_clkmr2:1;
 159                u32 swreset_clkmr1:1;
 160        } bits;
 161};
 162
 163int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
 164int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
 165
 166#endif /* _DCGU_H */
 167