uboot/board/st/stv0991/stv0991.c
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   1/*
   2 * (C) Copyright 2014
   3 * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <miiphy.h>
  10#include <asm/arch/stv0991_periph.h>
  11#include <asm/arch/stv0991_defs.h>
  12#include <asm/arch/hardware.h>
  13#include <asm/arch/gpio.h>
  14#include <netdev.h>
  15#include <asm/io.h>
  16#include <dm/platdata.h>
  17#include <dm/platform_data/serial_pl01x.h>
  18
  19DECLARE_GLOBAL_DATA_PTR;
  20
  21struct gpio_regs *const gpioa_regs =
  22                (struct gpio_regs *) GPIOA_BASE_ADDR;
  23
  24#ifndef CONFIG_OF_CONTROL
  25static const struct pl01x_serial_platdata serial_platdata = {
  26        .base = 0x80406000,
  27        .type = TYPE_PL011,
  28        .clock = 2700 * 1000,
  29};
  30
  31U_BOOT_DEVICE(stv09911_serials) = {
  32        .name = "serial_pl01x",
  33        .platdata = &serial_platdata,
  34};
  35#endif
  36
  37#ifdef CONFIG_SHOW_BOOT_PROGRESS
  38void show_boot_progress(int progress)
  39{
  40        printf("%i\n", progress);
  41}
  42#endif
  43
  44void enable_eth_phy(void)
  45{
  46        /* Set GPIOA_06 pad HIGH (Appli board)*/
  47        writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
  48        writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
  49}
  50int board_eth_enable(void)
  51{
  52        stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
  53        clock_setup(ETH_CLOCK_CFG);
  54        enable_eth_phy();
  55        return 0;
  56}
  57
  58int board_qspi_enable(void)
  59{
  60        stv0991_pinmux_config(QSPI_CS_CLK_PAD);
  61        clock_setup(QSPI_CLOCK_CFG);
  62        return 0;
  63}
  64
  65/*
  66 * Miscellaneous platform dependent initialisations
  67 */
  68int board_init(void)
  69{
  70        board_eth_enable();
  71        board_qspi_enable();
  72        return 0;
  73}
  74
  75int board_uart_init(void)
  76{
  77        stv0991_pinmux_config(UART_GPIOC_30_31);
  78        clock_setup(UART_CLOCK_CFG);
  79        return 0;
  80}
  81
  82#ifdef CONFIG_BOARD_EARLY_INIT_F
  83int board_early_init_f(void)
  84{
  85        board_uart_init();
  86        return 0;
  87}
  88#endif
  89
  90int dram_init(void)
  91{
  92        gd->ram_size = PHYS_SDRAM_1_SIZE;
  93        return 0;
  94}
  95
  96void dram_init_banksize(void)
  97{
  98        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  99        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 100}
 101
 102#ifdef CONFIG_CMD_NET
 103int board_eth_init(bd_t *bis)
 104{
 105        int ret = 0;
 106
 107#if defined(CONFIG_ETH_DESIGNWARE)
 108        u32 interface = PHY_INTERFACE_MODE_MII;
 109        if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
 110                ret++;
 111#endif
 112        return ret;
 113}
 114#endif
 115