1
2
3
4
5
6
7#ifndef _BEAGLE_H_
8#define _BEAGLE_H_
9
10#include <asm/arch/dss.h>
11
12const omap3_sysinfo sysinfo = {
13 DDR_STACKED,
14 "OMAP3 Beagle board",
15#if defined(CONFIG_ENV_IS_IN_ONENAND)
16 "OneNAND",
17#else
18 "NAND",
19#endif
20};
21
22
23#define REVISION_AXBX 0x7
24#define REVISION_CX 0x6
25#define REVISION_C4 0x5
26#define REVISION_XM_AB 0x0
27#define REVISION_XM_C 0x2
28
29
30
31
32
33
34
35
36
37
38
39#define MUX_BEAGLE() \
40 \
41 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
42 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
43 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
44 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
45 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
46 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
47 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
48 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
49 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
50 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
51 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
52 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
53 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
54 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
55 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
56 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
57 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
58 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
59 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
60 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
61 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
62 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
63 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
64 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
65 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
66 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
67 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
68 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
69 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
70 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
71 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
72 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
73 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
74 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
75 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
76 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
77 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
78 \
79 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) \
80 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) \
81 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) \
82 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) \
83 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) \
84 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) \
85 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) \
86 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) \
87 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) \
88 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) \
89 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) \
90 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) \
91 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) \
92 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) \
93 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) \
94 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) \
95 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) \
96 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) \
97 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) \
98 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) \
99 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) \
100 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) \
101 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) \
102 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) \
103 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) \
104 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) \
105 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
106 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
107 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
108 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
109 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) \
110 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) \
111 MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) \
112 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) \
113 MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) \
114 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) \
115 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
116 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) \
117 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
118 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
119 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
120 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) \
121 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
122 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
123 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
124 \
125 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
126 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
127 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
128 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
129 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
130 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
131 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
132 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
133 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
134 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
135 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
136 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
137 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
138 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
139 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
140 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
141 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
142 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
143 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
144 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
145 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
146 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
147 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
148 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
149 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
150 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
151 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
152 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
153 \
154 MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
155 MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
156 MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
157 MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
158 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) \
159 MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
160 MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
161 MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
162 MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
163 MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
164 MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
165 MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
166 MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
167 MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
168 MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
169 MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
170 MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
171 MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
172 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) \
173 MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
174 MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
175 MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
176 MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
177 MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
178 \
179 MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
180 MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
181 MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
182 MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
183 \
184 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) \
185 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) \
186 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) \
187 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) \
188 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) \
189 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) \
190 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) \
191 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) \
192 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) \
193 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) \
194 \
195 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) \
196 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) \
197 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) \
198 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) \
199 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
200 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) \
201 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) \
202 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \
203 MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) \
204 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) \
205 \
206 MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) \
207 MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) \
208 MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) \
209 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) \
210 MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) \
211 MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) \
212 MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) \
213 MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) \
214 \
215 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
216 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) \
217 MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) \
218 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
219 MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) \
220 MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) \
221 MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) \
222 MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) \
223 MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) \
224 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) \
225 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) \
226 MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) \
227 MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
228 MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) \
229 MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) \
230 \
231 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) \
232 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
233 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
234 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
235 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
236 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
237 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
238 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
239 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
240 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
241 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
242 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
243 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
244 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
245 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
246 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
247 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
248 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
249 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
250 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
251 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
252 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
253 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
254 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
255 MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) \
256 MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) \
257 MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) \
258 MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) \
259 MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
260 MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) \
261 MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) \
262 \
263 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) \
264 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) \
265 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) \
266 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) \
267 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) \
268 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) \
269 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) \
270 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) \
271 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) \
272 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) \
273 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)) \
274 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)) \
275 \
276 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
277 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
278 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
279 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
280 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
281 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
282 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
283 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
284 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) \
285 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) \
286 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
287 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
288 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) \
289 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) \
290 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) \
291 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) \
292 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) \
293 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) \
294 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) \
295 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) \
296 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) \
297 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) \
298 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) \
299 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) \
300 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) \
301 MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) \
302 MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) \
303 MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) \
304 MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) \
305 MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) \
306 MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) \
307 MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) \
308 MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) \
309 MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) \
310 MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) \
311 MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) \
312 MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) \
313 MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) \
314 MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) \
315 MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) \
316 MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) \
317 MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) \
318 MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) \
319 MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) \
320 MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) \
321 MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) \
322 MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) \
323 MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) \
324 MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) \
325 MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) \
326 MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) \
327 MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) \
328 MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) \
329 MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) \
330 MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) \
331 MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) \
332 MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) \
333 MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) \
334 MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
335 MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
336 MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
337 MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
338 MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
339 MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
340 MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
341 MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
342 MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
343 MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
344 MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
345 MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
346 MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
347 MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
348 MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
349 MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
350 MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
351 MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
352 MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
353 MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
354 MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
355 MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
356 MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
357 MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
358 MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
359 MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
360 MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
361 MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
362 MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
363 MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
364 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) \
365 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0))
366
367#define MUX_BEAGLE_C() \
368 MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) \
369 MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) \
370 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) \
371 MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
372 MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
373 MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
374 MUX_VAL(CP(UART2_RX), (IDIS | PTU | EN | M4))
375
376#define MUX_BEAGLE_XM() \
377 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) \
378 MUX_VAL(CP(GPMC_WAIT1), (IDIS | PTU | EN | M4)) \
379 MUX_VAL(CP(MMC1_DAT7), (IDIS | PTU | EN | M4)) \
380 MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) \
381 MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) \
382 MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) \
383 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) \
384 MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
385 MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
386 MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
387 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) \
388 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) \
389 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) \
390 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) \
391 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) \
392 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) \
393 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) \
394 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) \
395 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) \
396 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) \
397 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) \
398 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) \
399 MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) \
400 MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) \
401 MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) \
402 MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) \
403 MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) \
404 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3))
405
406#define MUX_TINCANTOOLS_ZIPPY() \
407 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) \
408 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) \
409 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) \
410 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) \
411 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) \
412 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) \
413 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) \
414 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) \
415 MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) \
416 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) \
417 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | EN | M1)) \
418 MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) \
419 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M1)) \
420 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) \
421 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) \
422 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) \
423 MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) \
424 MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) \
425 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4))
426
427#define MUX_TINCANTOOLS_TRAINER() \
428 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) \
429 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) \
430 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) \
431 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) \
432 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
433 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) \
434 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) \
435 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \
436 MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) \
437 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) \
438 MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
439 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
440 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4))
441
442#define MUX_KBADC_BEAGLEFPGA() \
443 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) \
444 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) \
445 MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) \
446 MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1))
447
448#define MUX_BBTOYS_WIFI() \
449 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) \
450 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) \
451 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) \
452 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) \
453 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) \
454 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) \
455 MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
456 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \
457 MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
458 MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4))
459
460
461
462
463
464#define DVI_BEAGLE_ORANGE_COL 0x00FF8000
465#define VENC_HEIGHT 0x00ef
466#define VENC_WIDTH 0x027f
467
468
469
470
471
472
473static const struct venc_regs venc_config_std_tv = {
474 .status = 0x0000001B,
475 .f_control = 0x00000040,
476 .vidout_ctrl = 0x00000000,
477 .sync_ctrl = 0x00008000,
478 .llen = 0x00008359,
479 .flens = 0x0000020C,
480 .hfltr_ctrl = 0x00000000,
481 .cc_carr_wss_carr = 0x043F2631,
482 .c_phase = 0x00000024,
483 .gain_u = 0x00000130,
484 .gain_v = 0x00000198,
485 .gain_y = 0x000001C0,
486 .black_level = 0x0000006A,
487 .blank_level = 0x0000005C,
488 .x_color = 0x00000000,
489 .m_control = 0x00000001,
490 .bstamp_wss_data = 0x0000003F,
491 .s_carr = 0x21F07C1F,
492 .line21 = 0x00000000,
493 .ln_sel = 0x00000015,
494 .l21__wc_ctl = 0x00001400,
495 .htrigger_vtrigger = 0x00000000,
496 .savid__eavid = 0x069300F4,
497 .flen__fal = 0x0016020C,
498 .lal__phase_reset = 0x00060107,
499 .hs_int_start_stop_x = 0x008D034E,
500 .hs_ext_start_stop_x = 0x000F0359,
501 .vs_int_start_x = 0x01A00000,
502 .vs_int_stop_x__vs_int_start_y = 0x020501A0,
503 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
504 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
505 .vs_ext_stop_y = 0x00000006,
506 .avid_start_stop_x = 0x03480079,
507 .avid_start_stop_y = 0x02040024,
508 .fid_int_start_x__fid_int_start_y = 0x0001008A,
509 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
510 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
511 .tvdetgp_int_start_stop_x = 0x00140001,
512 .tvdetgp_int_start_stop_y = 0x00010001,
513 .gen_ctrl = 0x00FF0000,
514 .output_control = 0x0000000D,
515 .dac_b__dac_c = 0x00000000
516};
517
518
519
520
521static const struct panel_config dvid_cfg = {
522 .timing_h = 0x0ff03f31,
523 .timing_v = 0x01400504,
524 .pol_freq = 0x00007028,
525 .divisor = 0x00010006,
526 .lcd_size = 0x02ff03ff,
527 .panel_type = 0x01,
528 .data_lines = 0x03,
529 .load_mode = 0x02,
530 .panel_color = DVI_BEAGLE_ORANGE_COL,
531 .gfx_format = GFXFORMAT_RGB24_UNPACKED,
532};
533
534static const struct panel_config dvid_cfg_xm = {
535 .timing_h = 0x1a4024c9,
536 .timing_v = 0x02c00509,
537 .pol_freq = 0x00007028,
538 .divisor = 0x00010001,
539 .lcd_size = 0x02ff03ff,
540 .panel_type = 0x01,
541 .data_lines = 0x03,
542 .load_mode = 0x02,
543 .panel_color = DVI_BEAGLE_ORANGE_COL,
544 .gfx_format = GFXFORMAT_RGB24_UNPACKED,
545};
546#endif
547