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14#include <common.h>
15#include <console.h>
16#include <virtex2.h>
17
18#if 0
19#define FPGA_DEBUG
20#endif
21
22#ifdef FPGA_DEBUG
23#define PRINTF(fmt,args...) printf (fmt ,##args)
24#else
25#define PRINTF(fmt,args...)
26#endif
27
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29
30
31
32
33
34#ifndef CONFIG_SYS_FPGA_CHECK_BUSY
35#undef CONFIG_SYS_FPGA_CHECK_BUSY
36#endif
37
38#ifndef CONFIG_FPGA_DELAY
39#define CONFIG_FPGA_DELAY()
40#endif
41
42#ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
43#define CONFIG_SYS_FPGA_PROG_FEEDBACK
44#endif
45
46
47
48
49#ifndef CONFIG_SYS_FPGA_CHECK_CTRLC
50#undef CONFIG_SYS_FPGA_CHECK_CTRLC
51#endif
52
53
54
55
56#ifndef CONFIG_SYS_FPGA_CHECK_ERROR
57#define CONFIG_SYS_FPGA_CHECK_ERROR
58#endif
59
60
61
62
63
64
65
66
67
68#ifndef CONFIG_SYS_FPGA_WAIT_INIT
69#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2
70#endif
71
72
73
74
75
76
77#ifndef CONFIG_SYS_FPGA_WAIT_BUSY
78#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200
79#endif
80
81
82
83
84#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
85#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5
86#endif
87
88static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
89static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
90
91static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
92static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
93
94static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
95 bitstream_type bstype)
96{
97 int ret_val = FPGA_FAIL;
98
99 switch (desc->iface) {
100 case slave_serial:
101 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
102 ret_val = virtex2_ss_load(desc, buf, bsize);
103 break;
104
105 case slave_selectmap:
106 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
107 ret_val = virtex2_ssm_load(desc, buf, bsize);
108 break;
109
110 default:
111 printf ("%s: Unsupported interface type, %d\n",
112 __FUNCTION__, desc->iface);
113 }
114 return ret_val;
115}
116
117static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
118{
119 int ret_val = FPGA_FAIL;
120
121 switch (desc->iface) {
122 case slave_serial:
123 PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
124 ret_val = virtex2_ss_dump(desc, buf, bsize);
125 break;
126
127 case slave_parallel:
128 PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
129 ret_val = virtex2_ssm_dump(desc, buf, bsize);
130 break;
131
132 default:
133 printf ("%s: Unsupported interface type, %d\n",
134 __FUNCTION__, desc->iface);
135 }
136 return ret_val;
137}
138
139static int virtex2_info(xilinx_desc *desc)
140{
141 return FPGA_SUCCESS;
142}
143
144
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147
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153
154
155
156
157
158static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
159{
160 int ret_val = FPGA_FAIL;
161 xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
162
163 PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
164 __FUNCTION__, __LINE__, fn);
165
166 if (fn) {
167 size_t bytecount = 0;
168 unsigned char *data = (unsigned char *) buf;
169 int cookie = desc->cookie;
170 unsigned long ts;
171
172
173 PRINTF ("%s:%d: Function Table:\n"
174 " base 0x%p\n"
175 " struct 0x%p\n"
176 " pre 0x%p\n"
177 " prog 0x%p\n"
178 " init 0x%p\n"
179 " error 0x%p\n",
180 __FUNCTION__, __LINE__,
181 &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
182 PRINTF (" clock 0x%p\n"
183 " cs 0x%p\n"
184 " write 0x%p\n"
185 " rdata 0x%p\n"
186 " wdata 0x%p\n"
187 " busy 0x%p\n"
188 " abort 0x%p\n"
189 " post 0x%p\n\n",
190 fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
191 fn->busy, fn->abort, fn->post);
192
193#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
194 printf ("Initializing FPGA Device %d...\n", cookie);
195#endif
196
197
198
199 if (*fn->pre) {
200 (*fn->pre) (cookie);
201 }
202
203
204
205
206
207
208
209 (*fn->pgm) (true, true, cookie);
210 udelay (10);
211 ts = get_timer (0);
212 do {
213 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
214 printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
215 " to assert.\n", __FUNCTION__, __LINE__,
216 CONFIG_SYS_FPGA_WAIT_INIT);
217 (*fn->abort) (cookie);
218 return FPGA_FAIL;
219 }
220 } while (!(*fn->init) (cookie));
221
222 (*fn->pgm) (false, true, cookie);
223 CONFIG_FPGA_DELAY ();
224 (*fn->clk) (true, true, cookie);
225
226
227
228
229 ts = get_timer (0);
230 do {
231 CONFIG_FPGA_DELAY ();
232 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
233 printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
234 " to deassert.\n", __FUNCTION__, __LINE__,
235 CONFIG_SYS_FPGA_WAIT_INIT);
236 (*fn->abort) (cookie);
237 return FPGA_FAIL;
238 }
239 } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
240
241 (*fn->wr) (true, true, cookie);
242 (*fn->cs) (true, true, cookie);
243
244 udelay (10000);
245
246
247
248
249 while (bytecount < bsize) {
250#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
251 if (ctrlc ()) {
252 (*fn->abort) (cookie);
253 return FPGA_FAIL;
254 }
255#endif
256
257 if ((*fn->done) (cookie) == FPGA_SUCCESS) {
258 PRINTF ("%s:%d:done went active early, bytecount = %d\n",
259 __FUNCTION__, __LINE__, bytecount);
260 break;
261 }
262
263#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
264 if ((*fn->init) (cookie)) {
265 printf ("\n%s:%d: ** Error: INIT asserted during"
266 " configuration\n", __FUNCTION__, __LINE__);
267 printf ("%d = buffer offset, %d = buffer size\n",
268 bytecount, bsize);
269 (*fn->abort) (cookie);
270 return FPGA_FAIL;
271 }
272#endif
273
274 (*fn->wdata) (data[bytecount++], true, cookie);
275 CONFIG_FPGA_DELAY ();
276
277
278
279
280 (*fn->clk) (false, true, cookie);
281 CONFIG_FPGA_DELAY ();
282 (*fn->clk) (true, true, cookie);
283
284#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
285 ts = get_timer (0);
286 while ((*fn->busy) (cookie)) {
287 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
288 printf ("%s:%d: ** Timeout after %d ticks waiting for"
289 " BUSY to deassert\n",
290 __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY);
291 (*fn->abort) (cookie);
292 return FPGA_FAIL;
293 }
294 }
295#endif
296
297#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
298 if (bytecount % (bsize / 40) == 0)
299 putc ('.');
300#endif
301 }
302
303
304
305
306 CONFIG_FPGA_DELAY ();
307 (*fn->cs) (false, true, cookie);
308 (*fn->wr) (false, true, cookie);
309
310#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
311 putc ('\n');
312#endif
313
314
315
316
317
318 ts = get_timer (0);
319 ret_val = FPGA_SUCCESS;
320 while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) {
321 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
322 printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
323 "assert and INIT to deassert\n",
324 __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
325 (*fn->abort) (cookie);
326 ret_val = FPGA_FAIL;
327 break;
328 }
329 }
330
331 if (ret_val == FPGA_SUCCESS) {
332#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
333 printf ("Initialization of FPGA device %d complete\n", cookie);
334#endif
335
336
337
338 if (*fn->post) {
339 (*fn->post) (cookie);
340 }
341 } else {
342#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
343 printf ("** Initialization of FPGA device %d FAILED\n",
344 cookie);
345#endif
346 }
347 } else {
348 printf ("%s:%d: NULL Interface function table!\n",
349 __FUNCTION__, __LINE__);
350 }
351 return ret_val;
352}
353
354
355
356
357static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
358{
359 int ret_val = FPGA_FAIL;
360 xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
361
362 if (fn) {
363 unsigned char *data = (unsigned char *) buf;
364 size_t bytecount = 0;
365 int cookie = desc->cookie;
366
367 printf ("Starting Dump of FPGA Device %d...\n", cookie);
368
369 (*fn->cs) (true, true, cookie);
370 (*fn->clk) (true, true, cookie);
371
372 while (bytecount < bsize) {
373#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
374 if (ctrlc ()) {
375 (*fn->abort) (cookie);
376 return FPGA_FAIL;
377 }
378#endif
379
380
381
382 (*fn->clk) (false, true, cookie);
383 (*fn->clk) (true, true, cookie);
384 (*fn->rdata) (&(data[bytecount++]), cookie);
385#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
386 if (bytecount % (bsize / 40) == 0)
387 putc ('.');
388#endif
389 }
390
391
392
393
394 (*fn->cs) (false, false, cookie);
395 (*fn->clk) (false, true, cookie);
396 (*fn->clk) (true, true, cookie);
397
398#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
399 putc ('\n');
400#endif
401 puts ("Done.\n");
402 } else {
403 printf ("%s:%d: NULL Interface function table!\n",
404 __FUNCTION__, __LINE__);
405 }
406 return ret_val;
407}
408
409static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
410{
411 printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
412 return FPGA_FAIL;
413}
414
415static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
416{
417 printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
418 return FPGA_FAIL;
419}
420
421
422
423struct xilinx_fpga_op virtex2_op = {
424 .load = virtex2_load,
425 .dump = virtex2_dump,
426 .info = virtex2_info,
427};
428