1/* 2 * U-Boot - Configuration file for cm-bf548 board 3 */ 4 5#ifndef __CONFIG_CM_BF548_H__ 6#define __CONFIG_CM_BF548_H__ 7 8#include <asm/config-pre.h> 9 10/* 11 * Processor Settings 12 */ 13#define CONFIG_BFIN_CPU bf548-0.0 14#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA 15 16/* 17 * Clock Settings 18 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 19 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 20 */ 21/* CONFIG_CLKIN_HZ is any value in Hz */ 22#define CONFIG_CLKIN_HZ 25000000 23/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 24/* 1 = CLKIN / 2 */ 25#define CONFIG_CLKIN_HALF 0 26/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 27/* 1 = bypass PLL */ 28#define CONFIG_PLL_BYPASS 0 29/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 30/* Values can range from 0-63 (where 0 means 64) */ 31#define CONFIG_VCO_MULT 21 32/* CCLK_DIV controls the core clock divider */ 33/* Values can be 1, 2, 4, or 8 ONLY */ 34#define CONFIG_CCLK_DIV 1 35/* SCLK_DIV controls the system clock divider */ 36/* Values can range from 1-15 */ 37#define CONFIG_SCLK_DIV 4 38 39/* Decrease core voltage */ 40#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) 41 42/* 43 * Memory Settings 44 */ 45#define CONFIG_MEM_ADD_WDTH 10 46#define CONFIG_MEM_SIZE 64 47 48#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE 49#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 50#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 51 52/* Default bank mapping: 53 * Async Bank 0 - 32MB Burst Flash 54 * Async Bank 1 - Ethernet 55 * Async Bank 2 - Nothing 56 * Async Bank 3 - Nothing 57 */ 58#define CONFIG_EBIU_AMGCTL_VAL 0xFF 59#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 60#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 61#define CONFIG_EBIU_FCTL_VAL (BCLK_4) 62#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) 63 64#define CONFIG_SYS_MONITOR_LEN (512 * 1024) 65#define CONFIG_SYS_MALLOC_LEN (640 * 1024) 66 67/* 68 * Network Settings 69 */ 70#define ADI_CMDS_NETWORK 1 71#define CONFIG_SMC911X 1 72#define CONFIG_SMC911X_BASE 0x24000000 73#define CONFIG_SMC911X_16_BIT 74#define CONFIG_HOSTNAME cm-bf548 75 76/* 77 * Flash Settings 78 */ 79#define CONFIG_FLASH_CFI_DRIVER 80#define CONFIG_SYS_FLASH_BASE 0x20000000 81#define CONFIG_SYS_FLASH_CFI 82#define CONFIG_SYS_FLASH_PROTECTION 83#define CONFIG_SYS_MAX_FLASH_BANKS 1 84#define CONFIG_SYS_MAX_FLASH_SECT 259 85 86/* 87 * Env Storage Settings 88 */ 89#define CONFIG_ENV_IS_IN_FLASH 1 90#define CONFIG_ENV_ADDR 0x20008000 91#define CONFIG_ENV_OFFSET 0x8000 92#define CONFIG_ENV_SIZE 0x8000 93#define CONFIG_ENV_IS_EMBEDDED_IN_LDR 94 95/* 96 * I2C Settings 97 */ 98#define CONFIG_SYS_I2C 99#define CONFIG_SYS_I2C_ADI 100 101/* 102 * Misc Settings 103 */ 104#define CONFIG_BAUDRATE 115200 105#define CONFIG_BOARD_EARLY_INIT_F 106#define CONFIG_RTC_BFIN 107#define CONFIG_UART_CONSOLE 1 108#define CONFIG_BOOTCOMMAND "run flashboot" 109#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" 110 111#define CONFIG_ADI_GPIO2 112 113#ifndef __ADSPBF542__ 114/* Don't waste time transferring a logo over the UART */ 115# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) 116# define CONFIG_VIDEO 117# define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h> 118# endif 119# define CONFIG_DEB_DMA_URGENT 120#endif 121 122/* Define if want to do post memory test */ 123#undef CONFIG_POST 124#ifdef CONFIG_POST 125#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ 126#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ 127#endif 128 129/* 130 * Pull in common ADI header for remaining command/environment setup 131 */ 132#include <configs/bfin_adi_common.h> 133 134#endif 135