1/* 2 * Configuation settings for the Renesas Solutions ECOVEC board 3 * 4 * Copyright (C) 2009 - 2011 Renesas Solutions Corp. 5 * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11#ifndef __ECOVEC_H 12#define __ECOVEC_H 13 14/* 15 * Address Interface BusWidth 16 *----------------------------------------- 17 * 0x0000_0000 U-Boot 16bit 18 * 0x0004_0000 Linux romImage 16bit 19 * 0x0014_0000 MTD for Linux 16bit 20 * 0x0400_0000 Internal I/O 16/32bit 21 * 0x0800_0000 DRAM 32bit 22 * 0x1800_0000 MFI 16bit 23 */ 24 25#undef DEBUG 26#define CONFIG_CPU_SH7724 1 27#define CONFIG_BOARD_LATE_INIT 1 28#define CONFIG_ECOVEC 1 29 30#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000 31#define CONFIG_SYS_TEXT_BASE 0x8FFC0000 32 33#define CONFIG_CMD_SDRAM 34#define CONFIG_CMD_ENV 35 36#define CONFIG_DOS_PARTITION 37 38#define CONFIG_BAUDRATE 115200 39#define CONFIG_BOOTARGS "console=ttySC0,115200" 40 41#undef CONFIG_SHOW_BOOT_PROGRESS 42 43/* I2C */ 44#define CONFIG_SYS_I2C 45#define CONFIG_SYS_I2C_SH 46#define CONFIG_SYS_I2C_SLAVE 0x7F 47#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2 48#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000 49#define CONFIG_SYS_I2C_SH_SPEED0 100000 50#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000 51#define CONFIG_SYS_I2C_SH_SPEED1 100000 52#define CONFIG_SH_I2C_DATA_HIGH 4 53#define CONFIG_SH_I2C_DATA_LOW 5 54#define CONFIG_SH_I2C_CLOCK 41666666 55 56/* Ether */ 57#define CONFIG_SH_ETHER 1 58#define CONFIG_SH_ETHER_USE_PORT (0) 59#define CONFIG_SH_ETHER_PHY_ADDR (0x1f) 60#define CONFIG_PHY_SMSC 1 61#define CONFIG_PHYLIB 62#define CONFIG_BITBANGMII 63#define CONFIG_BITBANGMII_MULTI 64#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 65 66/* USB / R8A66597 */ 67#define CONFIG_USB_R8A66597_HCD 68#define CONFIG_R8A66597_BASE_ADDR 0xA4D80000 69#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 70#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 71#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 72#define CONFIG_SUPERH_ON_CHIP_R8A66597 73 74/* undef to save memory */ 75#define CONFIG_SYS_LONGHELP 76/* Monitor Command Prompt */ 77/* Buffer size for input from the Console */ 78#define CONFIG_SYS_CBSIZE 256 79/* Buffer size for Console output */ 80#define CONFIG_SYS_PBSIZE 256 81/* max args accepted for monitor commands */ 82#define CONFIG_SYS_MAXARGS 16 83/* Buffer size for Boot Arguments passed to kernel */ 84#define CONFIG_SYS_BARGSIZE 512 85/* List of legal baudrate settings for this board */ 86#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 87 88/* SCIF */ 89#define CONFIG_SCIF_CONSOLE 1 90#define CONFIG_SCIF 1 91#define CONFIG_CONS_SCIF0 1 92 93/* Suppress display of console information at boot */ 94#undef CONFIG_SYS_CONSOLE_INFO_QUIET 95#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 96#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 97 98/* SDRAM */ 99#define CONFIG_SYS_SDRAM_BASE (0x88000000) 100#define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024) 101#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 102 103#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 104#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024) 105/* Enable alternate, more extensive, memory test */ 106#undef CONFIG_SYS_ALT_MEMTEST 107/* Scratch address used by the alternate memory test */ 108#undef CONFIG_SYS_MEMTEST_SCRATCH 109 110/* Enable temporary baudrate change while serial download */ 111#undef CONFIG_SYS_LOADS_BAUD_CHANGE 112 113/* FLASH */ 114#define CONFIG_FLASH_CFI_DRIVER 1 115#define CONFIG_SYS_FLASH_CFI 116#undef CONFIG_SYS_FLASH_QUIET_TEST 117#define CONFIG_SYS_FLASH_EMPTY_INFO 118#define CONFIG_SYS_FLASH_BASE (0xA0000000) 119#define CONFIG_SYS_MAX_FLASH_SECT 512 120 121/* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 122#define CONFIG_SYS_MAX_FLASH_BANKS 1 123#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 124 125/* Timeout for Flash erase operations (in ms) */ 126#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 127/* Timeout for Flash write operations (in ms) */ 128#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 129/* Timeout for Flash set sector lock bit operations (in ms) */ 130#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 131/* Timeout for Flash clear lock bit operations (in ms) */ 132#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 133 134/* 135 * Use hardware flash sectors protection instead 136 * of U-Boot software protection 137 */ 138#undef CONFIG_SYS_FLASH_PROTECTION 139#undef CONFIG_SYS_DIRECT_FLASH_TFTP 140 141/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 142#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 143/* Monitor size */ 144#define CONFIG_SYS_MONITOR_LEN (256 * 1024) 145/* Size of DRAM reserved for malloc() use */ 146#define CONFIG_SYS_MALLOC_LEN (256 * 1024) 147#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 148 149/* ENV setting */ 150#define CONFIG_ENV_IS_IN_FLASH 151#define CONFIG_ENV_OVERWRITE 1 152#define CONFIG_ENV_SECT_SIZE (128 * 1024) 153#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 154#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 155/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 156#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 157#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 158 159/* Board Clock */ 160#define CONFIG_SYS_CLK_FREQ 41666666 161#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 162#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 163#define CONFIG_SYS_TMU_CLK_DIV 4 164 165#endif /* __ECOVEC_H */ 166