LXR uboot/include/configs/ls1043a

   1/*
   2 * Copyright (C) 2015 Freescale Semiconductor
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#ifndef __LS1043A_COMMON_H
   8#define __LS1043A_COMMON_H
   9
  10#define CONFIG_REMAKE_ELF
  11#define CONFIG_FSL_LAYERSCAPE
  12#define CONFIG_FSL_LSCH2
  13#define CONFIG_LS1043A
  14#define CONFIG_MP
  15#define CONFIG_SYS_FSL_CLK
  16#define CONFIG_GICV2
  17
  18#include <asm/arch/config.h>
  19#ifdef CONFIG_SYS_FSL_SRDS_1
  20#define CONFIG_SYS_HAS_SERDES
  21#endif
  22
  23/* Link Definitions */
  24#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  25
  26#define CONFIG_SUPPORT_RAW_INITRD
  27
  28#define CONFIG_SKIP_LOWLEVEL_INIT
  29#define CONFIG_BOARD_EARLY_INIT_F       1
  30
  31#ifndef CONFIG_SYS_FSL_DDR4
  32#define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
  33#endif
  34
  35#define CONFIG_VERY_BIG_RAM
  36#define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  37#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  38#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  39#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
  40
  41#define CPU_RELEASE_ADDR               secondary_boot_func
  42
  43/* Generic Timer Definitions */
  44#define COUNTER_FREQUENCY               25000000        /* 25MHz */
  45
  46/* Size of malloc() pool */
  47#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
  48
  49/* Serial Port */
  50#define CONFIG_CONS_INDEX               1
  51#define CONFIG_SYS_NS16550_SERIAL
  52#define CONFIG_SYS_NS16550_REG_SIZE     1
  53#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
  54
  55#define CONFIG_BAUDRATE                 115200
  56#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  57
  58/* SD boot SPL */
  59#ifdef CONFIG_SD_BOOT
  60#define CONFIG_SPL_FRAMEWORK
  61#define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  62#define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  63#define CONFIG_SPL_LIBCOMMON_SUPPORT
  64#define CONFIG_SPL_LIBGENERIC_SUPPORT
  65#define CONFIG_SPL_ENV_SUPPORT
  66#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  67#define CONFIG_SPL_WATCHDOG_SUPPORT
  68#define CONFIG_SPL_I2C_SUPPORT
  69#define CONFIG_SPL_SERIAL_SUPPORT
  70#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  71#define CONFIG_SPL_MMC_SUPPORT
  72#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xf0
  73#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x500
  74
  75#define CONFIG_SPL_TEXT_BASE            0x10000000
  76#define CONFIG_SPL_MAX_SIZE             0x1d000
  77#define CONFIG_SPL_STACK                0x1001e000
  78#define CONFIG_SPL_PAD_TO               0x1d000
  79
  80#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  81                                        CONFIG_SYS_MONITOR_LEN)
  82#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  83#define CONFIG_SPL_BSS_START_ADDR       0x80100000
  84#define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  85#define CONFIG_SYS_MONITOR_LEN          0xa0000
  86#endif
  87
  88/* NAND SPL */
  89#ifdef CONFIG_NAND_BOOT
  90#define CONFIG_SPL_PBL_PAD
  91#define CONFIG_SPL_FRAMEWORK
  92#define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  93#define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  94#define CONFIG_SPL_LIBCOMMON_SUPPORT
  95#define CONFIG_SPL_LIBGENERIC_SUPPORT
  96#define CONFIG_SPL_ENV_SUPPORT
  97#define CONFIG_SPL_WATCHDOG_SUPPORT
  98#define CONFIG_SPL_I2C_SUPPORT
  99#define CONFIG_SPL_SERIAL_SUPPORT
 100#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 101#define CONFIG_SPL_NAND_SUPPORT
 102#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 103#define CONFIG_SPL_TEXT_BASE            0x10000000
 104#define CONFIG_SPL_MAX_SIZE             0x1a000
 105#define CONFIG_SPL_STACK                0x1001d000
 106#define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 107#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 108#define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 109#define CONFIG_SPL_BSS_START_ADDR       0x80100000
 110#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 111#define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 112#define CONFIG_SYS_MONITOR_LEN          0xa0000
 113#endif
 114
 115/* IFC */
 116#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 117#define CONFIG_FSL_IFC
 118/*
 119 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 120 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 121 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 122 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 123 */
 124#define CONFIG_SYS_FLASH_BASE                   0x60000000
 125#define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 126#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 127
 128#ifndef CONFIG_SYS_NO_FLASH
 129#define CONFIG_FLASH_CFI_DRIVER
 130#define CONFIG_SYS_FLASH_CFI
 131#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 132#define CONFIG_SYS_FLASH_QUIET_TEST
 133#define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 134#endif
 135#endif
 136
 137/* I2C */
 138#define CONFIG_SYS_I2C
 139#define CONFIG_SYS_I2C_MXC
 140#define CONFIG_SYS_I2C_MXC_I2C1
 141#define CONFIG_SYS_I2C_MXC_I2C2
 142#define CONFIG_SYS_I2C_MXC_I2C3
 143#define CONFIG_SYS_I2C_MXC_I2C4
 144
 145/* PCIe */
 146#define CONFIG_PCI              /* Enable PCI/PCIE */
 147#define CONFIG_PCIE1            /* PCIE controller 1 */
 148#define CONFIG_PCIE2            /* PCIE controller 2 */
 149#define CONFIG_PCIE3            /* PCIE controller 3 */
 150#define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 151#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 152
 153#define CONFIG_SYS_PCI_64BIT
 154
 155#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 156#define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 157#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 158#define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 159
 160#define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 161#define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 162#define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 163
 164#define CONFIG_SYS_PCIE_MEM_BUS         0x40000000
 165#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x40000000
 166#define CONFIG_SYS_PCIE_MEM_SIZE        0x40000000      /* 1G */
 167
 168#ifdef CONFIG_PCI
 169#define CONFIG_NET_MULTI
 170#define CONFIG_PCI_PNP
 171#define CONFIG_E1000
 172#define CONFIG_PCI_SCAN_SHOW
 173#define CONFIG_CMD_PCI
 174#endif
 175
 176/* Command line configuration */
 177#define CONFIG_CMD_ENV
 178#define CONFIG_MENU
 179#define CONFIG_CMD_PXE
 180
 181/*  MMC  */
 182#define CONFIG_MMC
 183#ifdef CONFIG_MMC
 184#define CONFIG_FSL_ESDHC
 185#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 186#define CONFIG_GENERIC_MMC
 187#define CONFIG_DOS_PARTITION
 188#endif
 189
 190/*  DSPI  */
 191#define CONFIG_FSL_DSPI
 192#ifdef CONFIG_FSL_DSPI
 193#define CONFIG_DM_SPI_FLASH
 194#define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
 195#define CONFIG_SPI_FLASH_SST            /* cs1 */
 196#define CONFIG_SPI_FLASH_EON            /* cs2 */
 197#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 198#define CONFIG_SF_DEFAULT_BUS           1
 199#define CONFIG_SF_DEFAULT_CS            0
 200#endif
 201#endif
 202
 203#define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 204
 205/* FMan ucode */
 206#define CONFIG_SYS_DPAA_FMAN
 207#ifdef CONFIG_SYS_DPAA_FMAN
 208#define CONFIG_SYS_FM_MURAM_SIZE        0x60000
 209
 210#ifdef CONFIG_NAND_BOOT
 211/* Store Fman ucode at offeset 0x160000(11 blocks). */
 212#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 213#define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 214#elif defined(CONFIG_SD_BOOT)
 215/*
 216 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 217 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
 218 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
 219 */
 220#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 221#define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 222#elif defined(CONFIG_QSPI_BOOT)
 223#define CONFIG_SYS_QE_FW_IN_SPIFLASH
 224#define CONFIG_SYS_FMAN_FW_ADDR         0x400d0000
 225#define CONFIG_ENV_SPI_BUS              0
 226#define CONFIG_ENV_SPI_CS               0
 227#define CONFIG_ENV_SPI_MAX_HZ           1000000
 228#define CONFIG_ENV_SPI_MODE             0x03
 229#else
 230#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 231/* FMan fireware Pre-load address */
 232#define CONFIG_SYS_FMAN_FW_ADDR         0x60300000
 233#endif
 234#define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 235#define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 236#endif
 237
 238/* Miscellaneous configurable options */
 239#define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 240#define CONFIG_ARCH_EARLY_INIT_R
 241#define CONFIG_BOARD_LATE_INIT
 242
 243#define CONFIG_HWCONFIG
 244#define HWCONFIG_BUFFER_SIZE            128
 245
 246#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 247#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
 248                        "5m(kernel),1m(dtb),9m(file_system)"
 249#else
 250#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
 251                        "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
 252                        "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
 253                        "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
 254                        "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
 255                        "40m(nor_bank4_fit);7e800000.flash:" \
 256                        "1m(nand_uboot),1m(nand_uboot_env)," \
 257                        "20m(nand_fit);spi0.0:1m(uboot)," \
 258                        "5m(kernel),1m(dtb),9m(file_system)"
 259#endif
 260
 261/* Initial environment variables */
 262#define CONFIG_EXTRA_ENV_SETTINGS               \
 263        "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 264        "loadaddr=0x80100000\0"                 \
 265        "fdt_high=0xffffffffffffffff\0"         \
 266        "initrd_high=0xffffffffffffffff\0"      \
 267        "kernel_start=0x61100000\0"             \
 268        "kernel_load=0xa0000000\0"              \
 269        "kernel_size=0x2800000\0"               \
 270        "console=ttyS0,115200\0"                \
 271        "mtdparts=" MTDPARTS_DEFAULT "\0"
 272
 273#define CONFIG_BOOTARGS                 "console=ttyS0,115200 root=/dev/ram0 " \
 274                                        "earlycon=uart8250,mmio,0x21c0500 "    \
 275                                        MTDPARTS_DEFAULT
 276
 277#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 278#define CONFIG_BOOTCOMMAND              "sf probe && sf read $kernel_load "    \
 279                                        "e0000 f00000 && bootm $kernel_load"
 280#else
 281#define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 282                                        "$kernel_size && bootm $kernel_load"
 283#endif
 284
 285/* Monitor Command Prompt */
 286#define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 287#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 288                                        sizeof(CONFIG_SYS_PROMPT) + 16)
 289#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 290#define CONFIG_SYS_LONGHELP
 291#define CONFIG_CMDLINE_EDITING          1
 292#define CONFIG_AUTO_COMPLETE
 293#define CONFIG_SYS_MAXARGS              64      /* max command args */
 294
 295#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 296
 297/* Hash command with SHA acceleration supported in hardware */
 298#ifdef CONFIG_FSL_CAAM
 299#define CONFIG_CMD_HASH
 300#define CONFIG_SHA_HW_ACCEL
 301#endif
 302
 303#endif /* __LS1043A_COMMON_H */
 304