LXR uboot/include/configs/t3corp.h

   1/*
   2 * (C) Copyright 2010
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*
   9 * t3corp.h - configuration for T3CORP (460GT)
  10 */
  11#ifndef __CONFIG_H
  12#define __CONFIG_H
  13
  14/*
  15 * High Level Configuration Options
  16 */
  17#define CONFIG_460GT            1       /* Specific PPC460GT    */
  18#define CONFIG_440              1
  19
  20#ifndef CONFIG_SYS_TEXT_BASE
  21#define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  22#endif
  23
  24#define CONFIG_HOSTNAME         t3corp
  25
  26/*
  27 * Include common defines/options for all AMCC/APM eval boards
  28 */
  29#include "amcc-common.h"
  30
  31#define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
  32
  33#define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_early_init_f */
  34#define CONFIG_BOARD_EARLY_INIT_R       1       /* Call board_early_init_r */
  35#define CONFIG_MISC_INIT_R              1       /* Call misc_init_r */
  36#define CONFIG_BOARD_TYPES              1       /* support board types */
  37#define CFG_ALT_MEMTEST
  38
  39/*
  40 * Base addresses -- Note these are effective addresses where the
  41 * actual resources get mapped (not physical addresses)
  42 */
  43#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory */
  44#define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs */
  45#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  46
  47#define CONFIG_SYS_PCIE_MEMBASE         0xb0000000      /* mapped PCIe mem */
  48#define CONFIG_SYS_PCIE_MEMSIZE         0x08000000      /* incr for PCIe */
  49#define CONFIG_SYS_PCIE_BASE            0xc4000000      /* PCIe UTL regs */
  50
  51#define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  52#define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  53#define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  54#define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  55
  56#define CONFIG_SYS_PCIE0_UTLBASE        0xc08010000ULL  /* 36bit phys addr */
  57
  58/* base address of inbound PCIe window */
  59#define CONFIG_SYS_PCIE_INBOUND_BASE    0x000000000ULL  /* 36bit phys addr */
  60
  61/* EBC stuff */
  62#define CONFIG_SYS_FLASH_BASE           0xFC000000      /* later mapped here */
  63#define CONFIG_SYS_FLASH_SIZE           (64 << 20)
  64
  65#define CONFIG_SYS_FPGA1_BASE           0xe0000000
  66#define CONFIG_SYS_FPGA2_BASE           0xe2000000
  67#define CONFIG_SYS_FPGA3_BASE           0xe4000000
  68
  69#define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space */
  70#define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
  71#define CONFIG_SYS_FLASH_BASE_PHYS_L    0xCC000000
  72#define CONFIG_SYS_FLASH_BASE_PHYS \
  73        (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
  74        | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
  75
  76#define CONFIG_SYS_OCM_BASE             0xE7000000      /* OCM: 64k */
  77#define CONFIG_SYS_SRAM_BASE            0xE8000000      /* SRAM: 256k */
  78#define CONFIG_SYS_SRAM_SIZE            (256 << 10)
  79#define CONFIG_SYS_LOCAL_CONF_REGS      0xEF000000
  80
  81/*
  82 * Initial RAM & stack pointer (placed in OCM)
  83 */
  84#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM */
  85#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  86#define CONFIG_SYS_GBL_DATA_OFFSET \
  87        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  88#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  89
  90/*
  91 * Serial Port
  92 */
  93#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  94
  95/*
  96 * Environment
  97 */
  98/*
  99 * Define here the location of the environment variables (flash).
 100 */
 101#define CONFIG_ENV_IS_IN_FLASH          /* use flash for environment vars */
 102
 103/*
 104 * Flash related
 105 */
 106#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 107#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 108#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 109#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 110#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method      */
 111#define CONFIG_SYS_FLASH_PROTECTION     /* use hardware flash protection */
 112
 113#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, \
 114                        (CONFIG_SYS_FPGA1_BASE + 0x01000000) }
 115#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff,      /* don't set    */ \
 116                        0xbddf }                /* set async read mode  */
 117#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks */
 118#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors p. chip*/
 119
 120#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms*/
 121#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms*/
 122
 123#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buff'd writes (20x faster)*/
 124#define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 125
 126#define CONFIG_ENV_SECT_SIZE            0x20000 /* sector size */
 127#define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - \
 128                                         CONFIG_ENV_SECT_SIZE)
 129#define CONFIG_ENV_SIZE                 0x4000  /* env sector size */
 130
 131/* Address and size of Redundant Environment Sector     */
 132#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 133#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 134
 135/*
 136 * DDR2 SDRAM
 137 */
 138#define CONFIG_SYS_MBYTES_SDRAM         256
 139#define CONFIG_DDR_ECC
 140#define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
 141#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration   */
 142#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 143#undef CONFIG_PPC4xx_DDR_METHOD_A
 144#define CONFIG_DDR_RFDC_FIXED           0x000001D7 /* optimal value */
 145
 146/* DDR1/2 SDRAM Device Control Register Data Values */
 147/* Memory Queue */
 148#define CONFIG_SYS_SDRAM_R0BAS          (SDRAM_RXBAS_SDBA_ENCODE(0) | \
 149                                         SDRAM_RXBAS_SDSZ_256)
 150#define CONFIG_SYS_SDRAM_R1BAS          0x00000000
 151#define CONFIG_SYS_SDRAM_R2BAS          0x00000000
 152#define CONFIG_SYS_SDRAM_R3BAS          0x00000000
 153#define CONFIG_SYS_SDRAM_PLBADDULL      0x00000000
 154#define CONFIG_SYS_SDRAM_PLBADDUHB      0x00000008
 155#define CONFIG_SYS_SDRAM_CONF1LL        0x80001C00
 156#define CONFIG_SYS_SDRAM_CONF1HB        0x80001C80
 157#define CONFIG_SYS_SDRAM_CONFPATHB      0x10a68000
 158
 159#define CAS_LATENCY                     JEDEC_MA_MR_CL_DDR2_5_0_CLK
 160
 161/* DDR1/2 SDRAM Device Control Register Data Values */
 162#define CONFIG_SYS_SDRAM0_MB0CF         (SDRAM_RXBAS_SDAM_MODE7         | \
 163                                         SDRAM_RXBAS_SDBE_ENABLE)
 164#define CONFIG_SYS_SDRAM0_MB1CF         SDRAM_RXBAS_SDBE_DISABLE
 165#define CONFIG_SYS_SDRAM0_MB2CF         SDRAM_RXBAS_SDBE_DISABLE
 166#define CONFIG_SYS_SDRAM0_MB3CF         SDRAM_RXBAS_SDBE_DISABLE
 167#define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_MCHK_GEN          | \
 168                                         SDRAM_MCOPT1_PMU_OPEN          | \
 169                                         SDRAM_MCOPT1_DMWD_32           | \
 170                                         SDRAM_MCOPT1_8_BANKS           | \
 171                                         SDRAM_MCOPT1_DDR2_TYPE         | \
 172                                         SDRAM_MCOPT1_QDEP              | \
 173                                         SDRAM_MCOPT1_RWOO_DISABLED     | \
 174                                         SDRAM_MCOPT1_WOOO_DISABLED     | \
 175                                         SDRAM_MCOPT1_DREF_NORMAL)
 176#define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 177#define CONFIG_SYS_SDRAM0_MODT0         SDRAM_MODT_EB0W_ENABLE
 178#define CONFIG_SYS_SDRAM0_MODT1         0x00000000
 179#define CONFIG_SYS_SDRAM0_MODT2         0x00000000
 180#define CONFIG_SYS_SDRAM0_MODT3         0x00000000
 181#define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON             | \
 182                                         SDRAM_CODT_DQS_1_8_V_DDR2      | \
 183                                         SDRAM_CODT_IO_NMODE)
 184#define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
 185#define CONFIG_SYS_SDRAM0_INITPLR0                                      \
 186        (SDRAM_INITPLR_ENABLE                                           | \
 187         SDRAM_INITPLR_IMWT_ENCODE(80)                                  | \
 188         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
 189#define CONFIG_SYS_SDRAM0_INITPLR1                                      \
 190        (SDRAM_INITPLR_ENABLE                                           | \
 191         SDRAM_INITPLR_IMWT_ENCODE(3)                                   | \
 192         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)                 | \
 193         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                          | \
 194         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 195#define CONFIG_SYS_SDRAM0_INITPLR2                                      \
 196        (SDRAM_INITPLR_ENABLE                                           | \
 197         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 198         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 199         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                        | \
 200         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
 201#define CONFIG_SYS_SDRAM0_INITPLR3                                      \
 202        (SDRAM_INITPLR_ENABLE                                           | \
 203         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 204         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 205         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                        | \
 206         SDRAM_INITPLR_IMA_ENCODE(0))
 207#define CONFIG_SYS_SDRAM0_INITPLR4                                      \
 208        (SDRAM_INITPLR_ENABLE                                           | \
 209         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 210         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 211         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                         | \
 212         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE               | \
 213                                  JEDEC_MA_EMR_RTT_150OHM))
 214#define CONFIG_SYS_SDRAM0_INITPLR5                                      \
 215        (SDRAM_INITPLR_ENABLE                                           | \
 216         SDRAM_INITPLR_IMWT_ENCODE(200)                                 | \
 217         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 218         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                          | \
 219         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC             | \
 220                                  CAS_LATENCY                           | \
 221                                  JEDEC_MA_MR_BLEN_4                    | \
 222                                  JEDEC_MA_MR_DLL_RESET))
 223#define CONFIG_SYS_SDRAM0_INITPLR6                                      \
 224        (SDRAM_INITPLR_ENABLE                                           | \
 225         SDRAM_INITPLR_IMWT_ENCODE(3)                                   | \
 226         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)                 | \
 227         SDRAM_INITPLR_IBA_ENCODE(0x0)                                  | \
 228         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 229#define CONFIG_SYS_SDRAM0_INITPLR7                                      \
 230        (SDRAM_INITPLR_ENABLE                                           | \
 231         SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 232         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 233#define CONFIG_SYS_SDRAM0_INITPLR8                                      \
 234        (SDRAM_INITPLR_ENABLE                                           | \
 235         SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 236         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 237#define CONFIG_SYS_SDRAM0_INITPLR9                                      \
 238        (SDRAM_INITPLR_ENABLE                                           | \
 239         SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 240         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 241#define CONFIG_SYS_SDRAM0_INITPLR10                                     \
 242        (SDRAM_INITPLR_ENABLE                                           | \
 243         SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 244         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 245#define CONFIG_SYS_SDRAM0_INITPLR11                                     \
 246        (SDRAM_INITPLR_ENABLE                                           | \
 247         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 248         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 249         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                          | \
 250         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC             | \
 251                                  CAS_LATENCY                           | \
 252                                  JEDEC_MA_MR_BLEN_4))
 253#define CONFIG_SYS_SDRAM0_INITPLR12                                     \
 254        (SDRAM_INITPLR_ENABLE                                           | \
 255         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 256         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 257         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                         | \
 258         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER                | \
 259                                  JEDEC_MA_EMR_RDQS_DISABLE             | \
 260                                  JEDEC_MA_EMR_DQS_ENABLE               | \
 261                                  JEDEC_MA_EMR_RTT_150OHM               | \
 262                                  JEDEC_MA_EMR_ODS_NORMAL))
 263#define CONFIG_SYS_SDRAM0_INITPLR13                                     \
 264        (SDRAM_INITPLR_ENABLE                                           | \
 265         SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 266         SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 267         SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                         | \
 268         SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT                 | \
 269                                  JEDEC_MA_EMR_RDQS_DISABLE             | \
 270                                  JEDEC_MA_EMR_DQS_ENABLE               | \
 271                                  JEDEC_MA_EMR_RTT_150OHM               | \
 272                                  JEDEC_MA_EMR_ODS_NORMAL))
 273#define CONFIG_SYS_SDRAM0_INITPLR14     SDRAM_INITPLR_DISABLE
 274#define CONFIG_SYS_SDRAM0_INITPLR15     SDRAM_INITPLR_DISABLE
 275#define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE         | \
 276                                         SDRAM_RQDC_RQFD_ENCODE(56))
 277#define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(599)
 278#define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
 279#define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO           | \
 280                                         SDRAM_DLCR_DLCS_CONT_DONE      | \
 281                                         SDRAM_DLCR_DLCV_ENCODE(155))
 282#define CONFIG_SYS_SDRAM0_CLKTR         SDRAM_CLKTR_CLKP_90_DEG_ADV
 283#define CONFIG_SYS_SDRAM0_WRDTR         SDRAM_WRDTR_WTR_90_DEG_ADV
 284#define CONFIG_SYS_SDRAM0_SDTR1         (SDRAM_SDTR1_LDOF_2_CLK         | \
 285                                         SDRAM_SDTR1_RTW_2_CLK          | \
 286                                         SDRAM_SDTR1_RTRO_1_CLK)
 287#define CONFIG_SYS_SDRAM0_SDTR2         (SDRAM_SDTR2_RCD_3_CLK          | \
 288                                         SDRAM_SDTR2_WTR_2_CLK          | \
 289                                         SDRAM_SDTR2_XSNR_32_CLK        | \
 290                                         SDRAM_SDTR2_WPC_4_CLK          | \
 291                                         SDRAM_SDTR2_RPC_2_CLK          | \
 292                                         SDRAM_SDTR2_RP_3_CLK           | \
 293                                         SDRAM_SDTR2_RRD_2_CLK)
 294#define CONFIG_SYS_SDRAM0_SDTR3         (SDRAM_SDTR3_RAS_ENCODE(8)      | \
 295                                         SDRAM_SDTR3_RC_ENCODE(11)      | \
 296                                         SDRAM_SDTR3_XCS                | \
 297                                         SDRAM_SDTR3_RFC_ENCODE(26))
 298#define CONFIG_SYS_SDRAM0_MMODE         (SDRAM_MMODE_WR_DDR2_3_CYC      | \
 299                                         CAS_LATENCY                    | \
 300                                         SDRAM_MMODE_BLEN_4)
 301#define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_ENABLE        | \
 302                                         SDRAM_MEMODE_RTT_150OHM)
 303
 304/*
 305 * I2C
 306 */
 307#define CONFIG_SYS_I2C_PPC4XX_SPEED_0                   400000
 308
 309#define CONFIG_SYS_I2C_EEPROM_ADDR              (0xa8>>1)
 310#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 311#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 312#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 313
 314/* I2C bootstrap EEPROM */
 315#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 316#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 317#define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 318
 319/*
 320 * Ethernet
 321 */
 322#define CONFIG_IBM_EMAC4_V4     1
 323
 324#define CONFIG_HAS_ETH0
 325
 326#define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 327#define CONFIG_M88E1111_PHY
 328/* Disable fiber since fiber/copper auto-selection doesn't seem to work */
 329#define CONFIG_M88E1111_DISABLE_FIBER
 330
 331#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 332#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 333#define CONFIG_PHY_DYNAMIC_ANEG 1
 334
 335/*
 336 * Default environment variables
 337 */
 338#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 339        CONFIG_AMCC_DEF_ENV                                             \
 340        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 341        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 342        "kernel_addr=fc000000\0"                                        \
 343        "fdt_addr=fc1e0000\0"                                           \
 344        "ramdisk_addr=fc200000\0"                                       \
 345        "pciconfighost=1\0"                                             \
 346        "pcie_mode=RP:RP\0"                                             \
 347        "unlock=yes\0"                                                  \
 348        ""
 349
 350/*
 351 * Commands additional to the ones defined in amcc-common.h
 352 */
 353#define CONFIG_CMD_CHIP_CONFIG
 354#define CONFIG_CMD_ECCTEST
 355#define CONFIG_CMD_PCI
 356#define CONFIG_CMD_SDRAM
 357
 358/*
 359 * PCI stuff
 360 */
 361/* General PCI */
 362#define CONFIG_PCI                      /* include pci support          */
 363#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 364#define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 365#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 366#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 367
 368/* Board-specific PCI, no PCI support, only PCIe */
 369#undef CONFIG_SYS_PCI_TARGET_INIT
 370#undef CONFIG_SYS_PCI_MASTER_INIT
 371
 372#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM */
 373#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 374
 375/*
 376 * External Bus Controller (EBC) Setup
 377 */
 378
 379/*
 380 * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
 381 * boot EBC mapping only supports a maximum of 16MBytes
 382 * (4.ff00.0000 - 4.ffff.ffff).
 383 * To solve this problem, the flash has to get remapped to another
 384 * EBC address which accepts bigger regions:
 385 *
 386 * 0xfc00.0000 -> 4.cc00.0000
 387 */
 388
 389/* Memory Bank 0 (NOR-flash) */
 390#define CONFIG_SYS_EBC_PB0AP    (EBC_BXAP_BME_DISABLED          |       \
 391                                 EBC_BXAP_TWT_ENCODE(16)        |       \
 392                                 EBC_BXAP_BCE_DISABLE           |       \
 393                                 EBC_BXAP_BCT_2TRANS            |       \
 394                                 EBC_BXAP_CSN_ENCODE(1)         |       \
 395                                 EBC_BXAP_OEN_ENCODE(1)         |       \
 396                                 EBC_BXAP_WBN_ENCODE(1)         |       \
 397                                 EBC_BXAP_WBF_ENCODE(1)         |       \
 398                                 EBC_BXAP_TH_ENCODE(7)          |       \
 399                                 EBC_BXAP_RE_DISABLED           |       \
 400                                 EBC_BXAP_SOR_DELAYED           |       \
 401                                 EBC_BXAP_BEM_WRITEONLY         |       \
 402                                 EBC_BXAP_PEN_DISABLED)
 403#define CONFIG_SYS_EBC_PB0CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \
 404                                 EBC_BXCR_BS_16MB               |       \
 405                                 EBC_BXCR_BU_RW                 |       \
 406                                 EBC_BXCR_BW_16BIT)
 407
 408/* Memory Bank 1 (FPGA 1) */
 409#define CONFIG_SYS_EBC_PB1AP    (EBC_BXAP_BME_DISABLED          |       \
 410                                 EBC_BXAP_TWT_ENCODE(5)         |       \
 411                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 412                                 EBC_BXAP_OEN_ENCODE(3)         |       \
 413                                 EBC_BXAP_WBN_ENCODE(0)         |       \
 414                                 EBC_BXAP_WBF_ENCODE(0)         |       \
 415                                 EBC_BXAP_TH_ENCODE(1)          |       \
 416                                 EBC_BXAP_RE_ENABLED            |       \
 417                                 EBC_BXAP_SOR_DELAYED           |       \
 418                                 EBC_BXAP_BEM_RW                |       \
 419                                 EBC_BXAP_PEN_DISABLED)
 420#define CONFIG_SYS_EBC_PB1CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
 421                                 EBC_BXCR_BS_32MB               |       \
 422                                 EBC_BXCR_BU_RW                 |       \
 423                                 EBC_BXCR_BW_32BIT)
 424
 425/* Memory Bank 2 (FPGA 2) */
 426#define CONFIG_SYS_EBC_PB2AP    (EBC_BXAP_BME_DISABLED          |       \
 427                                 EBC_BXAP_TWT_ENCODE(5)         |       \
 428                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 429                                 EBC_BXAP_OEN_ENCODE(3)         |       \
 430                                 EBC_BXAP_WBN_ENCODE(0)         |       \
 431                                 EBC_BXAP_WBF_ENCODE(0)         |       \
 432                                 EBC_BXAP_TH_ENCODE(1)          |       \
 433                                 EBC_BXAP_RE_ENABLED            |       \
 434                                 EBC_BXAP_SOR_DELAYED           |       \
 435                                 EBC_BXAP_BEM_RW                |       \
 436                                 EBC_BXAP_PEN_DISABLED)
 437#define CONFIG_SYS_EBC_PB2CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
 438                                 EBC_BXCR_BS_16MB               |       \
 439                                 EBC_BXCR_BU_RW                 |       \
 440                                 EBC_BXCR_BW_32BIT)
 441
 442/* Memory Bank 3 (FPGA 3) */
 443#define CONFIG_SYS_EBC_PB3AP    (EBC_BXAP_BME_DISABLED          |       \
 444                                 EBC_BXAP_TWT_ENCODE(5)         |       \
 445                                 EBC_BXAP_CSN_ENCODE(0)         |       \
 446                                 EBC_BXAP_OEN_ENCODE(3)         |       \
 447                                 EBC_BXAP_WBN_ENCODE(0)         |       \
 448                                 EBC_BXAP_WBF_ENCODE(0)         |       \
 449                                 EBC_BXAP_TH_ENCODE(1)          |       \
 450                                 EBC_BXAP_RE_ENABLED            |       \
 451                                 EBC_BXAP_SOR_DELAYED           |       \
 452                                 EBC_BXAP_BEM_RW                |       \
 453                                 EBC_BXAP_PEN_DISABLED)
 454#define CONFIG_SYS_EBC_PB3CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
 455                                 EBC_BXCR_BS_16MB               |       \
 456                                 EBC_BXCR_BU_RW                 |       \
 457                                 EBC_BXCR_BW_32BIT)
 458
 459/*
 460 * PPC4xx GPIO Configuration
 461 */
 462
 463#define CONFIG_SYS_4xx_GPIO_TABLE { /*            GPIO  Alternate1      Alternate2      Alternate3 */ \
 464{                                                                                       \
 465/* GPIO Core 0 */                                                                       \
 466{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 467{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 468{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 469{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 470{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 471{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 472{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 473{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 474{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 475{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 476{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 477{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 478{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 479{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 480{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 481{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 482{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 483{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 484{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 485{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 486{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 487{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 488{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 489{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 490{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 491{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 492{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 493{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 494{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 495{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 496{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 497{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 498},                                                                                      \
 499{                                                                                       \
 500/* GPIO Core 1 */                                                                       \
 501{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 502{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 503{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 504{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 505{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 506{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 507{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 508{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 509{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 510{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 511{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 512{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 513{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 514{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 515{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 516{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 517{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 518{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 519{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 520{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 521{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 522{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 523{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 524{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 525{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 526{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 527{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 528{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 529{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 530{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 531{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 532{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 533}                                                                                       \
 534}
 535
 536#endif  /* __CONFIG_H */
 537