LXR uboot/include/spd.h

   1/*
   2 * Copyright (C) 2003 Arabella Software Ltd.
   3 * Yuli Barcohen <yuli@arabellasw.com>
   4 *
   5 * Serial Presence Detect (SPD) EEPROM format according to the
   6 * Intel's PC SDRAM Serial Presence Detect (SPD) Specification,
   7 * revision 1.2B, November 1999
   8 *
   9 * SPDX-License-Identifier:     GPL-2.0+
  10 */
  11
  12#ifndef _SPD_H_
  13#define _SPD_H_
  14
  15typedef struct spd_eeprom_s {
  16        unsigned char info_size;   /*  0 # bytes written into serial memory */
  17        unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
  18        unsigned char mem_type;    /*  2 Fundamental memory type */
  19        unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
  20        unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
  21        unsigned char nrows;       /*  5 # of Module Rows on this assembly */
  22        unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
  23        unsigned char dataw_msb;   /*  7 ... Data Width continuation */
  24        unsigned char voltage;     /*  8 Voltage intf std of this assembly */
  25        unsigned char clk_cycle;   /*  9 SDRAM Cycle time at CL=X */
  26        unsigned char clk_access;  /* 10 SDRAM Access from Clock at CL=X */
  27        unsigned char config;      /* 11 DIMM Configuration type */
  28        unsigned char refresh;     /* 12 Refresh Rate/Type */
  29        unsigned char primw;       /* 13 Primary SDRAM Width */
  30        unsigned char ecw;         /* 14 Error Checking SDRAM width */
  31        unsigned char min_delay;   /* 15 for Back to Back Random Address */
  32        unsigned char burstl;      /* 16 Burst Lengths Supported */
  33        unsigned char nbanks;      /* 17 # of Banks on Each SDRAM Device */
  34        unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
  35        unsigned char cs_lat;      /* 19 CS# Latency */
  36        unsigned char write_lat;   /* 20 Write Latency (aka Write Recovery) */
  37        unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
  38        unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
  39        unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time at CL=X-1 */
  40        unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
  41        unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time at CL=X-2 */
  42        unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */
  43        unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
  44        unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
  45        unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
  46        unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
  47        unsigned char row_dens;    /* 31 Density of each row on module */
  48        unsigned char ca_setup;    /* 32 Cmd + Addr signal input setup time */
  49        unsigned char ca_hold;     /* 33 Cmd and Addr signal input hold time */
  50        unsigned char data_setup;  /* 34 Data signal input setup time */
  51        unsigned char data_hold;   /* 35 Data signal input hold time */
  52        unsigned char twr;         /* 36 Write Recovery time tWR */
  53        unsigned char twtr;        /* 37 Int write to read delay tWTR */
  54        unsigned char trtp;        /* 38 Int read to precharge delay tRTP */
  55        unsigned char mem_probe;   /* 39 Mem analysis probe characteristics */
  56        unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
  57        unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
  58        unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
  59        unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
  60        unsigned char tdqsq;       /* 44 Max DQS to DQ skew */
  61        unsigned char tqhs;        /* 45 Max Read DataHold skew tQHS */
  62        unsigned char pll_relock;  /* 46 PLL Relock time */
  63        unsigned char res[15];     /* 47-xx IDD in SPD and Reserved space */
  64        unsigned char spd_rev;     /* 62 SPD Data Revision Code */
  65        unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
  66        unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-108E */
  67        unsigned char mloc;        /* 72 Manufacturing Location */
  68        unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
  69        unsigned char rev[2];      /* 91 Revision Code */
  70        unsigned char mdate[2];    /* 93 Manufacturing Date */
  71        unsigned char sernum[4];   /* 95 Assembly Serial Number */
  72        unsigned char mspec[27];   /* 99 Manufacturer Specific Data */
  73
  74        /*
  75         * Open for Customer Use starting with byte 128.
  76         */
  77        unsigned char freq;        /* 128 Intel spec: frequency */
  78        unsigned char intel_cas;   /* 129 Intel spec: CAS# Latency support */
  79} spd_eeprom_t;
  80
  81
  82/*
  83 * Byte 2 Fundamental Memory Types.
  84 */
  85#define SPD_MEMTYPE_FPM         (0x01)
  86#define SPD_MEMTYPE_EDO         (0x02)
  87#define SPD_MEMTYPE_PIPE_NIBBLE (0x03)
  88#define SPD_MEMTYPE_SDRAM       (0x04)
  89#define SPD_MEMTYPE_ROM         (0x05)
  90#define SPD_MEMTYPE_SGRAM       (0x06)
  91#define SPD_MEMTYPE_DDR         (0x07)
  92#define SPD_MEMTYPE_DDR2        (0x08)
  93
  94#endif /* _SPD_H_ */
  95