1/* 2 * sun8i H3 platform dram controller register and constant defines 3 * 4 * (C) Copyright 2007-2015 Allwinner Technology Co. 5 * Jerry Wang <wangflord@allwinnertech.com> 6 * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> 7 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> 8 * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13#ifndef _SUNXI_DRAM_SUN8I_H3_H 14#define _SUNXI_DRAM_SUN8I_H3_H 15 16struct sunxi_mctl_com_reg { 17 u32 cr; /* 0x00 control register */ 18 u8 res0[0xc]; /* 0x04 */ 19 u32 mcr[16][2]; /* 0x10 */ 20 u32 bwcr; /* 0x90 bandwidth control register */ 21 u32 maer; /* 0x94 master enable register */ 22 u32 mapr; /* 0x98 master priority register */ 23 u32 mcgcr; /* 0x9c */ 24 u32 cpu_bwcr; /* 0xa0 */ 25 u32 gpu_bwcr; /* 0xa4 */ 26 u32 ve_bwcr; /* 0xa8 */ 27 u32 disp_bwcr; /* 0xac */ 28 u32 other_bwcr; /* 0xb0 */ 29 u32 total_bwcr; /* 0xb4 */ 30 u8 res1[0x8]; /* 0xb8 */ 31 u32 swonr; /* 0xc0 */ 32 u32 swoffr; /* 0xc4 */ 33 u8 res2[0x8]; /* 0xc8 */ 34 u32 cccr; /* 0xd0 */ 35 u8 res3[0x72c]; /* 0xd4 */ 36 u32 protect; /* 0x800 */ 37}; 38 39#define MCTL_CR_BL8 (0x4 << 20) 40 41#define MCTL_CR_1T (0x1 << 19) 42#define MCTL_CR_2T (0x0 << 19) 43 44#define MCTL_CR_LPDDR3 (0x7 << 16) 45#define MCTL_CR_LPDDR2 (0x6 << 16) 46#define MCTL_CR_DDR3 (0x3 << 16) 47#define MCTL_CR_DDR2 (0x2 << 16) 48 49#define MCTL_CR_SEQUENTIAL (0x1 << 15) 50#define MCTL_CR_INTERLEAVED (0x0 << 15) 51 52#define MCTL_CR_32BIT (0x1 << 12) 53#define MCTL_CR_16BIT (0x0 << 12) 54#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT) 55 56#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) 57#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) 58#define MCTL_CR_EIGHT_BANKS (0x1 << 2) 59#define MCTL_CR_FOUR_BANKS (0x0 << 2) 60#define MCTL_CR_DUAL_RANK (0x1 << 0) 61#define MCTL_CR_SINGLE_RANK (0x0 << 0) 62 63#define PROTECT_MAGIC (0x94be6fa3) 64 65struct sunxi_mctl_ctl_reg { 66 u32 pir; /* 0x00 PHY initialization register */ 67 u32 pwrctl; /* 0x04 */ 68 u32 mrctrl; /* 0x08 */ 69 u32 clken; /* 0x0c */ 70 u32 pgsr[2]; /* 0x10 PHY general status registers */ 71 u32 statr; /* 0x18 */ 72 u8 res1[0x14]; /* 0x1c */ 73 u32 mr[4]; /* 0x30 mode registers */ 74 u32 pllgcr; /* 0x40 */ 75 u32 ptr[5]; /* 0x44 PHY timing registers */ 76 u32 dramtmg[9]; /* 0x58 DRAM timing registers */ 77 u32 odtcfg; /* 0x7c */ 78 u32 pitmg[2]; /* 0x80 PHY interface timing registers */ 79 u8 res2[0x4]; /* 0x88 */ 80 u32 rfshctl0; /* 0x8c */ 81 u32 rfshtmg; /* 0x90 refresh timing */ 82 u32 rfshctl1; /* 0x94 */ 83 u32 pwrtmg; /* 0x98 */ 84 u8 res3[0x20]; /* 0x9c */ 85 u32 dqsgmr; /* 0xbc */ 86 u32 dtcr; /* 0xc0 */ 87 u32 dtar[4]; /* 0xc4 */ 88 u32 dtdr[2]; /* 0xd4 */ 89 u32 dtmr[2]; /* 0xdc */ 90 u32 dtbmr; /* 0xe4 */ 91 u32 catr[2]; /* 0xe8 */ 92 u32 dtedr[2]; /* 0xf0 */ 93 u8 res4[0x8]; /* 0xf8 */ 94 u32 pgcr[4]; /* 0x100 PHY general configuration registers */ 95 u32 iovcr[2]; /* 0x110 */ 96 u32 dqsdr; /* 0x118 */ 97 u32 dxccr; /* 0x11c */ 98 u32 odtmap; /* 0x120 */ 99 u32 zqctl[2]; /* 0x124 */ 100 u8 res6[0x14]; /* 0x12c */ 101 u32 zqcr; /* 0x140 ZQ control register */ 102 u32 zqsr; /* 0x144 ZQ status register */ 103 u32 zqdr[3]; /* 0x148 ZQ data registers */ 104 u8 res7[0x6c]; /* 0x154 */ 105 u32 sched; /* 0x1c0 */ 106 u32 perfhpr[2]; /* 0x1c4 */ 107 u32 perflpr[2]; /* 0x1cc */ 108 u32 perfwr[2]; /* 0x1d4 */ 109 u8 res8[0x2c]; /* 0x1dc */ 110 u32 aciocr; /* 0x208 */ 111 u8 res9[0xf4]; /* 0x20c */ 112 struct { /* 0x300 DATX8 modules*/ 113 u32 mdlr; /* 0x00 */ 114 u32 lcdlr[3]; /* 0x04 */ 115 u32 iocr[11]; /* 0x10 IO configuration register */ 116 u32 bdlr6; /* 0x3c */ 117 u32 gtr; /* 0x40 */ 118 u32 gcr; /* 0x44 */ 119 u32 gsr[3]; /* 0x48 */ 120 u8 res0[0x2c]; /* 0x54 */ 121 } datx[4]; 122 u8 res10[0x388]; /* 0x500 */ 123 u32 upd2; /* 0x888 */ 124}; 125 126#define PTR3_TDINIT1(x) ((x) << 20) 127#define PTR3_TDINIT0(x) ((x) << 0) 128 129#define PTR4_TDINIT3(x) ((x) << 20) 130#define PTR4_TDINIT2(x) ((x) << 0) 131 132#define DRAMTMG0_TWTP(x) ((x) << 24) 133#define DRAMTMG0_TFAW(x) ((x) << 16) 134#define DRAMTMG0_TRAS_MAX(x) ((x) << 8) 135#define DRAMTMG0_TRAS(x) ((x) << 0) 136 137#define DRAMTMG1_TXP(x) ((x) << 16) 138#define DRAMTMG1_TRTP(x) ((x) << 8) 139#define DRAMTMG1_TRC(x) ((x) << 0) 140 141#define DRAMTMG2_TCWL(x) ((x) << 24) 142#define DRAMTMG2_TCL(x) ((x) << 16) 143#define DRAMTMG2_TRD2WR(x) ((x) << 8) 144#define DRAMTMG2_TWR2RD(x) ((x) << 0) 145 146#define DRAMTMG3_TMRW(x) ((x) << 16) 147#define DRAMTMG3_TMRD(x) ((x) << 12) 148#define DRAMTMG3_TMOD(x) ((x) << 0) 149 150#define DRAMTMG4_TRCD(x) ((x) << 24) 151#define DRAMTMG4_TCCD(x) ((x) << 16) 152#define DRAMTMG4_TRRD(x) ((x) << 8) 153#define DRAMTMG4_TRP(x) ((x) << 0) 154 155#define DRAMTMG5_TCKSRX(x) ((x) << 24) 156#define DRAMTMG5_TCKSRE(x) ((x) << 16) 157#define DRAMTMG5_TCKESR(x) ((x) << 8) 158#define DRAMTMG5_TCKE(x) ((x) << 0) 159 160#define RFSHTMG_TREFI(x) ((x) << 16) 161#define RFSHTMG_TRFC(x) ((x) << 0) 162 163#define PIR_CLRSR (0x1 << 27) /* clear status registers */ 164#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */ 165#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */ 166#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */ 167#define PIR_PHYRST (0x1 << 6) /* PHY reset */ 168#define PIR_DCAL (0x1 << 5) /* DDL calibration */ 169#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */ 170#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */ 171#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */ 172 173#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */ 174 175#define ZQCR_PWRDOWN (0x1 << 31) /* ZQ power down */ 176 177#define DATX_IOCR_DQ(x) (x) /* DQ0-7 IOCR index */ 178#define DATX_IOCR_DM (8) /* DM IOCR index */ 179#define DATX_IOCR_DQS (9) /* DQS IOCR index */ 180#define DATX_IOCR_DQSN (10) /* DQSN IOCR index */ 181 182#define DATX_IOCR_WRITE_DELAY(x) ((x) << 8) 183#define DATX_IOCR_READ_DELAY(x) ((x) << 0) 184 185#endif /* _SUNXI_DRAM_SUN8I_H3_H */ 186