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8
9#include <common.h>
10#include <errno.h>
11#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/tegra.h>
14#include <asm/arch-tegra/ap.h>
15#include <asm/arch-tegra/clk_rst.h>
16#include <asm/arch-tegra/pmc.h>
17#include <asm/arch-tegra/timer.h>
18#include <div64.h>
19#include <fdtdec.h>
20
21
22
23
24
25
26static unsigned pll_rate[CLOCK_ID_COUNT];
27
28
29
30
31
32static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
33 13000000,
34 19200000,
35 12000000,
36 26000000,
37 38400000,
38 48000000,
39};
40
41
42#define clock_type_id_isvalid(id) ((id) >= 0 && \
43 (id) < CLOCK_TYPE_COUNT)
44
45char pllp_valid = 1;
46
47
48#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
49 (id) < PERIPHC_COUNT)
50
51
52static const u8 pll_num_clkouts[] = {
53 1,
54 1,
55 4,
56 1,
57 0,
58 0,
59};
60
61int clock_get_osc_bypass(void)
62{
63 struct clk_rst_ctlr *clkrst =
64 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
65 u32 reg;
66
67 reg = readl(&clkrst->crc_osc_ctrl);
68 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
69}
70
71
72static struct clk_pll *get_pll(enum clock_id clkid)
73{
74 struct clk_rst_ctlr *clkrst =
75 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
76
77 assert(clock_id_is_pll(clkid));
78 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
79 debug("%s: Invalid PLL %d\n", __func__, clkid);
80 return NULL;
81 }
82 return &clkrst->crc_pll[clkid];
83}
84
85__weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
86{
87 return NULL;
88}
89
90int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
91 u32 *divp, u32 *cpcon, u32 *lfcon)
92{
93 struct clk_pll *pll = get_pll(clkid);
94 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
95 u32 data;
96
97 assert(clkid != CLOCK_ID_USB);
98
99
100 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
101 return -1;
102 data = readl(&pll->pll_base);
103 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
104 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
105 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
106 data = readl(&pll->pll_misc);
107
108 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
109 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
110
111 return 0;
112}
113
114unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
115 u32 divp, u32 cpcon, u32 lfcon)
116{
117 struct clk_pll *pll = NULL;
118 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
119 struct clk_pll_simple *simple_pll = NULL;
120 u32 misc_data, data;
121
122 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
123 pll = get_pll(clkid);
124 } else {
125 simple_pll = clock_get_simple_pll(clkid);
126 if (!simple_pll) {
127 debug("%s: Uknown simple PLL %d\n", __func__, clkid);
128 return 0;
129 }
130 }
131
132
133
134
135
136
137
138
139 if (pll)
140 misc_data = readl(&pll->pll_misc);
141 else
142 misc_data = readl(&simple_pll->pll_misc);
143 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
144 misc_data |= cpcon << pllinfo->kcp_shift;
145 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
146 misc_data |= lfcon << pllinfo->kvco_shift;
147
148 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
149 data |= divp << pllinfo->p_shift;
150 data |= (1 << PLL_ENABLE_SHIFT);
151
152 if (pll) {
153 writel(misc_data, &pll->pll_misc);
154 writel(data, &pll->pll_base);
155 } else {
156 writel(misc_data, &simple_pll->pll_misc);
157 writel(data, &simple_pll->pll_base);
158 }
159
160
161 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
162}
163
164void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
165 unsigned divisor)
166{
167 u32 *reg = get_periph_source_reg(periph_id);
168 u32 value;
169
170 value = readl(reg);
171
172 value &= ~OUT_CLK_SOURCE_31_30_MASK;
173 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
174
175 value &= ~OUT_CLK_DIVISOR_MASK;
176 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
177
178 writel(value, reg);
179}
180
181int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
182 unsigned source)
183{
184 u32 *reg = get_periph_source_reg(periph_id);
185
186 switch (mux_bits) {
187 case MASK_BITS_31_30:
188 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
189 source << OUT_CLK_SOURCE_31_30_SHIFT);
190 break;
191
192 case MASK_BITS_31_29:
193 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
194 source << OUT_CLK_SOURCE_31_29_SHIFT);
195 break;
196
197 case MASK_BITS_31_28:
198 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
199 source << OUT_CLK_SOURCE_31_28_SHIFT);
200 break;
201
202 default:
203 return -1;
204 }
205
206 return 0;
207}
208
209static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
210{
211 u32 *reg = get_periph_source_reg(periph_id);
212 u32 val = readl(reg);
213
214 switch (mux_bits) {
215 case MASK_BITS_31_30:
216 val >>= OUT_CLK_SOURCE_31_30_SHIFT;
217 val &= OUT_CLK_SOURCE_31_30_MASK;
218 return val;
219 case MASK_BITS_31_29:
220 val >>= OUT_CLK_SOURCE_31_29_SHIFT;
221 val &= OUT_CLK_SOURCE_31_29_MASK;
222 return val;
223 case MASK_BITS_31_28:
224 val >>= OUT_CLK_SOURCE_31_28_SHIFT;
225 val &= OUT_CLK_SOURCE_31_28_MASK;
226 return val;
227 default:
228 return -1;
229 }
230}
231
232void clock_ll_set_source(enum periph_id periph_id, unsigned source)
233{
234 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
235}
236
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240
241
242
243
244
245
246static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
247 unsigned long rate)
248{
249 u64 divider = parent_rate * 2;
250 unsigned max_divider = 1 << divider_bits;
251
252 divider += rate - 1;
253 do_div(divider, rate);
254
255 if ((s64)divider - 2 < 0)
256 return 0;
257
258 if ((s64)divider - 2 >= max_divider)
259 return -1;
260
261 return divider - 2;
262}
263
264int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
265{
266 struct clk_pll *pll = get_pll(clkid);
267 int data = 0, div = 0, offset = 0;
268
269 if (!clock_id_is_pll(clkid))
270 return -1;
271
272 if (pllout + 1 > pll_num_clkouts[clkid])
273 return -1;
274
275 div = clk_get_divider(8, pll_rate[clkid], rate);
276
277 if (div < 0)
278 return -1;
279
280
281 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
282 offset = 16;
283
284 data = (div << PLL_OUT_RATIO_SHIFT) |
285 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
286 clrsetbits_le32(&pll->pll_out[pllout >> 1],
287 PLL_OUT_RATIO_MASK << offset, data << offset);
288
289 return 0;
290}
291
292
293
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297
298
299
300static unsigned long get_rate_from_divider(unsigned long parent_rate,
301 int divider)
302{
303 u64 rate;
304
305 rate = (u64)parent_rate * 2;
306 do_div(rate, divider + 2);
307 return rate;
308}
309
310unsigned long clock_get_periph_rate(enum periph_id periph_id,
311 enum clock_id parent)
312{
313 u32 *reg = get_periph_source_reg(periph_id);
314 unsigned parent_rate = pll_rate[parent];
315 int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT;
316
317 switch (periph_id) {
318 case PERIPH_ID_UART1:
319 case PERIPH_ID_UART2:
320 case PERIPH_ID_UART3:
321 case PERIPH_ID_UART4:
322 case PERIPH_ID_UART5:
323#ifdef CONFIG_TEGRA20
324
325 return parent_rate;
326#else
327
328
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339
340
341
342
343 div -= 2;
344 break;
345#endif
346 default:
347 break;
348 }
349
350 return get_rate_from_divider(parent_rate, div);
351}
352
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363
364
365
366static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
367 unsigned long rate, int *extra_div)
368{
369 int shift;
370 int best_divider = -1;
371 int best_error = rate;
372
373
374 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
375 unsigned divided_parent = parent_rate >> shift;
376 int divider = clk_get_divider(divider_bits, divided_parent,
377 rate);
378 unsigned effective_rate = get_rate_from_divider(divided_parent,
379 divider);
380 int error = rate - effective_rate;
381
382
383 if (divider != -1 && error < best_error) {
384 best_error = error;
385 *extra_div = 1 << shift;
386 best_divider = divider;
387 }
388 }
389
390
391 return best_divider;
392}
393
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402
403
404static int adjust_periph_pll(enum periph_id periph_id, int source,
405 int mux_bits, unsigned divider)
406{
407 u32 *reg = get_periph_source_reg(periph_id);
408
409 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
410 divider << OUT_CLK_DIVISOR_SHIFT);
411 udelay(1);
412
413
414 if (source < 0)
415 return -1;
416
417 clock_ll_set_source_bits(periph_id, mux_bits, source);
418
419 udelay(2);
420 return 0;
421}
422
423enum clock_id clock_get_periph_parent(enum periph_id periph_id)
424{
425 int err, mux_bits, divider_bits, type;
426 int source;
427
428 err = get_periph_clock_info(periph_id, &mux_bits, ÷r_bits, &type);
429 if (err)
430 return CLOCK_ID_NONE;
431
432 source = clock_ll_get_source_bits(periph_id, mux_bits);
433
434 return get_periph_clock_id(periph_id, source);
435}
436
437unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
438 enum clock_id parent, unsigned rate, int *extra_div)
439{
440 unsigned effective_rate;
441 int mux_bits, divider_bits, source;
442 int divider;
443 int xdiv = 0;
444
445
446 source = get_periph_clock_source(periph_id, parent, &mux_bits,
447 ÷r_bits);
448
449 divider = find_best_divider(divider_bits, pll_rate[parent],
450 rate, &xdiv);
451 if (extra_div)
452 *extra_div = xdiv;
453
454 assert(divider >= 0);
455 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
456 return -1U;
457 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
458 get_periph_source_reg(periph_id),
459 readl(get_periph_source_reg(periph_id)));
460
461
462 effective_rate = clock_get_periph_rate(periph_id, parent);
463 if (extra_div)
464 effective_rate /= *extra_div;
465 if (rate != effective_rate)
466 debug("Requested clock rate %u not honored (got %u)\n",
467 rate, effective_rate);
468 return effective_rate;
469}
470
471unsigned clock_start_periph_pll(enum periph_id periph_id,
472 enum clock_id parent, unsigned rate)
473{
474 unsigned effective_rate;
475
476 reset_set_enable(periph_id, 1);
477 clock_enable(periph_id);
478
479 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
480 NULL);
481
482 reset_set_enable(periph_id, 0);
483 return effective_rate;
484}
485
486void clock_enable(enum periph_id clkid)
487{
488 clock_set_enable(clkid, 1);
489}
490
491void clock_disable(enum periph_id clkid)
492{
493 clock_set_enable(clkid, 0);
494}
495
496void reset_periph(enum periph_id periph_id, int us_delay)
497{
498
499 reset_set_enable(periph_id, 1);
500 udelay(us_delay);
501
502
503 reset_set_enable(periph_id, 0);
504
505 udelay(us_delay);
506}
507
508void reset_cmplx_set_enable(int cpu, int which, int reset)
509{
510 struct clk_rst_ctlr *clkrst =
511 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
512 u32 mask;
513
514
515 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
516 mask = which << cpu;
517
518
519 if (reset)
520 writel(mask, &clkrst->crc_cpu_cmplx_set);
521 else
522 writel(mask, &clkrst->crc_cpu_cmplx_clr);
523}
524
525unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
526{
527 return parent_rate;
528}
529
530unsigned clock_get_rate(enum clock_id clkid)
531{
532 struct clk_pll *pll;
533 u32 base, divm;
534 u64 parent_rate, rate;
535 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
536
537 parent_rate = osc_freq[clock_get_osc_freq()];
538 if (clkid == CLOCK_ID_OSC)
539 return parent_rate;
540
541 if (clkid == CLOCK_ID_CLK_M)
542 return clk_m_get_rate(parent_rate);
543
544 pll = get_pll(clkid);
545 if (!pll)
546 return 0;
547 base = readl(&pll->pll_base);
548
549 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
550 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
551
552
553
554
555#ifdef CONFIG_TEGRA210
556
557
558
559
560
561
562 if (clkid != CLOCK_ID_PERIPH)
563#endif
564 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
565 do_div(rate, divm);
566 return rate;
567}
568
569
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572
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576
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578
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581
582
583
584
585
586int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
587{
588 u32 base_reg, misc_reg;
589 struct clk_pll *pll;
590 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
591
592 pll = get_pll(clkid);
593
594 base_reg = readl(&pll->pll_base);
595
596
597 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
598 base_reg |= m << pllinfo->m_shift;
599
600 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
601 base_reg |= n << pllinfo->n_shift;
602
603 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
604 base_reg |= p << pllinfo->p_shift;
605
606 if (clkid == CLOCK_ID_PERIPH) {
607
608
609
610
611 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
612 base_reg |= PLL_ENABLE_MASK;
613 if (base_reg != readl(&pll->pll_base))
614 pllp_valid = 0;
615 return pllp_valid ? 1 : -1;
616 }
617 base_reg |= PLL_BASE_OVRRIDE_MASK;
618 }
619
620 base_reg |= PLL_BYPASS_MASK;
621 writel(base_reg, &pll->pll_base);
622
623
624 misc_reg = readl(&pll->pll_misc);
625 misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
626 misc_reg |= cpcon << pllinfo->kcp_shift;
627 writel(misc_reg, &pll->pll_misc);
628
629
630 base_reg |= PLL_ENABLE_MASK;
631 writel(base_reg, &pll->pll_base);
632
633
634 base_reg &= ~PLL_BYPASS_MASK;
635 writel(base_reg, &pll->pll_base);
636
637 return 0;
638}
639
640void clock_ll_start_uart(enum periph_id periph_id)
641{
642
643 reset_set_enable(periph_id, 1);
644 clock_enable(periph_id);
645 clock_ll_set_source(periph_id, 0);
646
647
648 udelay(2);
649
650
651 reset_set_enable(periph_id, 0);
652}
653
654#if CONFIG_IS_ENABLED(OF_CONTROL)
655int clock_decode_periph_id(const void *blob, int node)
656{
657 enum periph_id id;
658 u32 cell[2];
659 int err;
660
661 err = fdtdec_get_int_array(blob, node, "clocks", cell,
662 ARRAY_SIZE(cell));
663 if (err)
664 return -1;
665 id = clk_id_to_periph_id(cell[1]);
666 assert(clock_periph_id_isvalid(id));
667 return id;
668}
669#endif
670
671int clock_verify(void)
672{
673 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
674 u32 reg = readl(&pll->pll_base);
675
676 if (!pllp_valid) {
677 printf("Warning: PLLP %x is not correct\n", reg);
678 return -1;
679 }
680 debug("PLLP %x is correct\n", reg);
681 return 0;
682}
683
684void clock_init(void)
685{
686 int i;
687
688 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
689 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
690 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
691 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
692 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
693 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
694 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
695 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
696 pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
697
698 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
699 debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
700 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
701 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
702 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
703 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
704 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
705 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
706
707 for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
708 enum periph_id periph_id;
709 enum clock_id parent;
710 int source, mux_bits, divider_bits;
711
712 periph_id = periph_clk_init_table[i].periph_id;
713 parent = periph_clk_init_table[i].parent_clock_id;
714
715 source = get_periph_clock_source(periph_id, parent, &mux_bits,
716 ÷r_bits);
717 clock_ll_set_source_bits(periph_id, mux_bits, source);
718 }
719}
720
721static void set_avp_clock_source(u32 src)
722{
723 struct clk_rst_ctlr *clkrst =
724 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
725 u32 val;
726
727 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
728 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
729 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
730 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
731 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
732 writel(val, &clkrst->crc_sclk_brst_pol);
733 udelay(3);
734}
735
736
737
738
739
740
741void tegra30_set_up_pllp(void)
742{
743 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
744 u32 reg;
745
746
747
748
749
750
751
752
753
754
755
756 set_avp_clock_source(SCLK_SOURCE_CLKM);
757
758
759
760
761
762 switch (clock_get_osc_freq()) {
763 case CLOCK_OSC_FREQ_12_0:
764 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
765 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
766 break;
767
768 case CLOCK_OSC_FREQ_26_0:
769 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
770 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
771 break;
772
773 case CLOCK_OSC_FREQ_13_0:
774 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
775 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
776 break;
777 case CLOCK_OSC_FREQ_19_2:
778 default:
779
780
781
782
783
784 break;
785 }
786
787
788
789
790
791 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
792 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
793
794 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
795 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
796 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
797 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
798 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
799
800
801
802 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
803 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
804
805 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
806 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
807 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
808 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
809 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
810
811 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
812}
813
814int clock_external_output(int clk_id)
815{
816 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
817
818 if (clk_id >= 1 && clk_id <= 3) {
819 setbits_le32(&pmc->pmc_clk_out_cntrl,
820 1 << (2 + (clk_id - 1) * 8));
821 } else {
822 printf("%s: Unknown output clock id %d\n", __func__, clk_id);
823 return -EINVAL;
824 }
825
826 return 0;
827}
828