1/* 2 * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef __FSL_SATA_H__ 9#define __FSL_SATA_H__ 10 11#define SATA_HC_MAX_NUM 4 /* Max host controller numbers */ 12#define SATA_HC_MAX_CMD 16 /* Max command queue depth per host controller */ 13#define SATA_HC_MAX_PORT 16 /* Max port number per host controller */ 14 15/* 16* SATA Host Controller Registers 17*/ 18typedef struct fsl_sata_reg { 19 /* SATA command registers */ 20 u32 cqr; /* Command queue register */ 21 u8 res1[0x4]; 22 u32 car; /* Command active register */ 23 u8 res2[0x4]; 24 u32 ccr; /* Command completed register */ 25 u8 res3[0x4]; 26 u32 cer; /* Command error register */ 27 u8 res4[0x4]; 28 u32 der; /* Device error register */ 29 u32 chba; /* Command header base address */ 30 u32 hstatus; /* Host status register */ 31 u32 hcontrol; /* Host control register */ 32 u32 cqpmp; /* Port number queue register */ 33 u32 sig; /* Signature register */ 34 u32 icc; /* Interrupt coalescing control register */ 35 u8 res5[0xc4]; 36 37 /* SATA supperset registers */ 38 u32 sstatus; /* SATA interface status register */ 39 u32 serror; /* SATA interface error register */ 40 u32 scontrol; /* SATA interface control register */ 41 u32 snotification; /* SATA interface notification register */ 42 u8 res6[0x30]; 43 44 /* SATA control status registers */ 45 u32 transcfg; /* Transport layer configuration */ 46 u32 transstatus; /* Transport layer status */ 47 u32 linkcfg; /* Link layer configuration */ 48 u32 linkcfg1; /* Link layer configuration1 */ 49 u32 linkcfg2; /* Link layer configuration2 */ 50 u32 linkstatus; /* Link layer status */ 51 u32 linkstatus1; /* Link layer status1 */ 52 u32 phyctrlcfg; /* PHY control configuration */ 53 u8 res7[0x2b0]; 54 55 /* SATA system control registers */ 56 u32 syspr; /* System priority register - big endian */ 57 u8 res8[0xbec]; 58} __attribute__ ((packed)) fsl_sata_reg_t; 59 60/* HStatus register 61*/ 62#define HSTATUS_ONOFF 0x80000000 /* Online/offline status */ 63#define HSTATUS_FORCE_OFFLINE 0x40000000 /* In process going offline */ 64#define HSTATUS_BIST_ERR 0x20000000 65 66/* Fatal error */ 67#define HSTATUS_MASTER_ERR 0x00004000 68#define HSTATUS_DATA_UNDERRUN 0x00002000 69#define HSTATUS_DATA_OVERRUN 0x00001000 70#define HSTATUS_CRC_ERR_TX 0x00000800 71#define HSTATUS_CRC_ERR_RX 0x00000400 72#define HSTATUS_FIFO_OVERFLOW_TX 0x00000200 73#define HSTATUS_FIFO_OVERFLOW_RX 0x00000100 74#define HSTATUS_FATAL_ERR_ALL (HSTATUS_MASTER_ERR | \ 75 HSTATUS_DATA_UNDERRUN | \ 76 HSTATUS_DATA_OVERRUN | \ 77 HSTATUS_CRC_ERR_TX | \ 78 HSTATUS_CRC_ERR_RX | \ 79 HSTATUS_FIFO_OVERFLOW_TX | \ 80 HSTATUS_FIFO_OVERFLOW_RX) 81/* Interrupt status */ 82#define HSTATUS_FATAL_ERR 0x00000020 83#define HSTATUS_PHY_RDY 0x00000010 84#define HSTATUS_SIGNATURE 0x00000008 85#define HSTATUS_SNOTIFY 0x00000004 86#define HSTATUS_DEVICE_ERR 0x00000002 87#define HSTATUS_CMD_COMPLETE 0x00000001 88 89/* HControl register 90*/ 91#define HCONTROL_ONOFF 0x80000000 /* Online or offline request */ 92#define HCONTROL_FORCE_OFFLINE 0x40000000 /* Force offline request */ 93#define HCONTROL_ENTERPRISE_EN 0x10000000 /* Enterprise mode enabled */ 94#define HCONTROL_HDR_SNOOP 0x00000400 /* Command header snoop */ 95#define HCONTROL_PMP_ATTACHED 0x00000200 /* Port multiplier attached */ 96 97/* Interrupt enable */ 98#define HCONTROL_FATAL_ERR 0x00000020 99#define HCONTROL_PHY_RDY 0x00000010 100#define HCONTROL_SIGNATURE 0x00000008 101#define HCONTROL_SNOTIFY 0x00000004 102#define HCONTROL_DEVICE_ERR 0x00000002 103#define HCONTROL_CMD_COMPLETE 0x00000001 104 105#define HCONTROL_INT_EN_ALL (HCONTROL_FATAL_ERR | \ 106 HCONTROL_PHY_RDY | \ 107 HCONTROL_SIGNATURE | \ 108 HCONTROL_SNOTIFY | \ 109 HCONTROL_DEVICE_ERR | \ 110 HCONTROL_CMD_COMPLETE) 111 112/* SStatus register 113*/ 114#define SSTATUS_IPM_MASK 0x00000780 115#define SSTATUS_IPM_NOPRESENT 0x00000000 116#define SSTATUS_IPM_ACTIVE 0x00000080 117#define SSTATUS_IPM_PATIAL 0x00000100 118#define SSTATUS_IPM_SLUMBER 0x00000300 119 120#define SSTATUS_SPD_MASK 0x000000f0 121#define SSTATUS_SPD_GEN1 0x00000010 122#define SSTATUS_SPD_GEN2 0x00000020 123 124#define SSTATUS_DET_MASK 0x0000000f 125#define SSTATUS_DET_NODEVICE 0x00000000 126#define SSTATUS_DET_DISCONNECT 0x00000001 127#define SSTATUS_DET_CONNECT 0x00000003 128#define SSTATUS_DET_PHY_OFFLINE 0x00000004 129 130/* SControl register 131*/ 132#define SCONTROL_SPM_MASK 0x0000f000 133#define SCONTROL_SPM_GO_PARTIAL 0x00001000 134#define SCONTROL_SPM_GO_SLUMBER 0x00002000 135#define SCONTROL_SPM_GO_ACTIVE 0x00004000 136 137#define SCONTROL_IPM_MASK 0x00000f00 138#define SCONTROL_IPM_NO_RESTRICT 0x00000000 139#define SCONTROL_IPM_PARTIAL 0x00000100 140#define SCONTROL_IPM_SLUMBER 0x00000200 141#define SCONTROL_IPM_PART_SLUM 0x00000300 142 143#define SCONTROL_SPD_MASK 0x000000f0 144#define SCONTROL_SPD_NO_RESTRICT 0x00000000 145#define SCONTROL_SPD_GEN1 0x00000010 146#define SCONTROL_SPD_GEN2 0x00000020 147 148#define SCONTROL_DET_MASK 0x0000000f 149#define SCONTROL_DET_HRESET 0x00000001 150#define SCONTROL_DET_DISABLE 0x00000004 151 152/* TransCfg register 153*/ 154#define TRANSCFG_DFIS_SIZE_SHIFT 16 155#define TRANSCFG_RX_WATER_MARK_MASK 0x0000001f 156 157/* PhyCtrlCfg register 158*/ 159#define PHYCTRLCFG_FPRFTI_MASK 0x00000018 160#define PHYCTRLCFG_LOOPBACK_MASK 0x0000000e 161 162/* 163* Command Header Entry 164*/ 165typedef struct cmd_hdr_entry { 166 __le32 cda; /* Command Descriptor Address, 167 4 bytes aligned */ 168 __le32 prde_fis_len; /* Number of PRD entries and FIS length */ 169 __le32 ttl; /* Total transfer length */ 170 __le32 attribute; /* the attribute of command */ 171} __attribute__ ((packed)) cmd_hdr_entry_t; 172 173#define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry) 174 175/* cda 176*/ 177#define CMD_HDR_CDA_ALIGN 4 178 179/* prde_fis_len 180*/ 181#define CMD_HDR_PRD_ENTRY_SHIFT 16 182#define CMD_HDR_PRD_ENTRY_MASK 0x003f0000 183#define CMD_HDR_FIS_LEN_SHIFT 2 184 185/* attribute 186*/ 187#define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */ 188#define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */ 189#define CMD_HDR_ATTR_SNOOP 0x00000200 /* Snoop enable for all descriptor */ 190#define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */ 191#define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */ 192#define CMD_HDR_ATTR_BIST 0x00000040 /* BIST - require the host to enter BIST mode */ 193#define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */ 194#define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */ 195 196/* command type 197*/ 198enum cmd_type { 199 CMD_VENDOR_BIST, 200 CMD_BIST, 201 CMD_RESET, /* SRST or device reset */ 202 CMD_ATAPI, 203 CMD_NCQ, 204 CMD_ATA, /* None of all above */ 205}; 206 207/* 208* Command Header Table 209*/ 210typedef struct cmd_hdr_tbl { 211 cmd_hdr_entry_t cmd_slot[SATA_HC_MAX_CMD]; 212} __attribute__ ((packed)) cmd_hdr_tbl_t; 213 214#define SATA_HC_CMD_HDR_TBL_SIZE sizeof(struct cmd_hdr_tbl) 215#define SATA_HC_CMD_HDR_TBL_ALIGN 4 216 217/* 218* PRD entry - Physical Region Descriptor entry 219*/ 220typedef struct prd_entry { 221 __le32 dba; /* Data base address, 4 bytes aligned */ 222 u32 res1; 223 u32 res2; 224 __le32 ext_c_ddc; /* Indirect PRD flags, snoop and data word count */ 225} __attribute__ ((packed)) prd_entry_t; 226 227#define SATA_HC_CMD_DESC_PRD_SIZE sizeof(struct prd_entry) 228 229/* dba 230*/ 231#define PRD_ENTRY_DBA_ALIGN 4 232 233/* ext_c_ddc 234*/ 235#define PRD_ENTRY_EXT 0x80000000 /* extension flag */ 236#ifdef CONFIG_FSL_SATA_V2 237#define PRD_ENTRY_DATA_SNOOP 0x10000000 /* Data snoop enable */ 238#else 239#define PRD_ENTRY_DATA_SNOOP 0x00400000 /* Data snoop enable */ 240#endif 241#define PRD_ENTRY_LEN_MASK 0x003fffff /* Data word count */ 242 243#define PRD_ENTRY_MAX_XFER_SZ (PRD_ENTRY_LEN_MASK + 1) 244 245/* 246 * This SATA host controller supports a max of 16 direct PRD entries, but if use 247 * chained indirect PRD entries, then the contollers supports upto a max of 63 248 * entries including direct and indirect PRD entries. 249 * The PRDT is an array of 63 PRD entries contigiously, but the PRD entries#15 250 * will be setup as an indirect descriptor, pointing to it's next (contigious) 251 * PRD entries#16. 252 */ 253#define SATA_HC_MAX_PRD 63 /* Max PRD entry numbers per command */ 254#define SATA_HC_MAX_PRD_DIRECT 16 /* Direct PRDT entries */ 255#define SATA_HC_MAX_PRD_USABLE (SATA_HC_MAX_PRD - 1) 256#define SATA_HC_MAX_XFER_LEN 0x4000000 257 258/* 259* PRDT - Physical Region Descriptor Table 260*/ 261typedef struct prdt { 262 prd_entry_t prdt[SATA_HC_MAX_PRD]; 263} __attribute__ ((packed)) prdt_t; 264 265/* 266* Command Descriptor 267*/ 268#define SATA_HC_CMD_DESC_CFIS_SIZE 32 /* bytes */ 269#define SATA_HC_CMD_DESC_SFIS_SIZE 32 /* bytes */ 270#define SATA_HC_CMD_DESC_ACMD_SIZE 16 /* bytes */ 271#define SATA_HC_CMD_DESC_RES 16 /* bytes */ 272 273typedef struct cmd_desc { 274 u8 cfis[SATA_HC_CMD_DESC_CFIS_SIZE]; 275 u8 sfis[SATA_HC_CMD_DESC_SFIS_SIZE]; 276 u8 acmd[SATA_HC_CMD_DESC_ACMD_SIZE]; 277 u8 res[SATA_HC_CMD_DESC_RES]; 278 prd_entry_t prdt[SATA_HC_MAX_PRD]; 279} __attribute__ ((packed)) cmd_desc_t; 280 281#define SATA_HC_CMD_DESC_SIZE sizeof(struct cmd_desc) 282#define SATA_HC_CMD_DESC_ALIGN 4 283 284/* 285 * SATA device driver info 286 */ 287typedef struct fsl_sata_info { 288 u32 sata_reg_base; 289 u32 flags; 290} fsl_sata_info_t; 291 292#define FLAGS_DMA 0x00000000 293#define FLAGS_FPDMA 0x00000001 294 295/* 296 * SATA device driver struct 297 */ 298typedef struct fsl_sata { 299 char name[12]; 300 fsl_sata_reg_t *reg_base; /* the base address of controller register */ 301 void *cmd_hdr_tbl_offset; /* alloc address of command header table */ 302 cmd_hdr_tbl_t *cmd_hdr; /* aligned address of command header table */ 303 void *cmd_desc_offset; /* alloc address of command descriptor */ 304 cmd_desc_t *cmd_desc; /* aligned address of command descriptor */ 305 int link; /* PHY link status */ 306 /* device attribute */ 307 int ata_device_type; /* device type */ 308 int lba48; 309 int queue_depth; /* Max NCQ queue depth */ 310 u16 pio; 311 u16 mwdma; 312 u16 udma; 313 int wcache; 314 int flush; 315 int flush_ext; 316} fsl_sata_t; 317 318#define READ_CMD 0 319#define WRITE_CMD 1 320 321#endif /* __FSL_SATA_H__ */ 322