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5
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10
11
12
13#define CONFIG_B4860QDS
14
15#ifdef CONFIG_RAMBOOT_PBL
16#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
17#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
18#ifndef CONFIG_NAND
19#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21#else
22#define CONFIG_SPL_FLUSH_IMAGE
23#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
24#define CONFIG_FSL_LAW
25#define CONFIG_SYS_TEXT_BASE 0x00201000
26#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
27#define CONFIG_SPL_PAD_TO 0x40000
28#define CONFIG_SPL_MAX_SIZE 0x28000
29#define RESET_VECTOR_OFFSET 0x27FFC
30#define BOOT_PAGE_OFFSET 0x27000
31#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
32#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
33#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
34#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
35#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
36#define CONFIG_SPL_NAND_BOOT
37#ifdef CONFIG_SPL_BUILD
38#define CONFIG_SPL_SKIP_RELOCATE
39#define CONFIG_SPL_COMMON_INIT_DDR
40#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
41#define CONFIG_SYS_NO_FLASH
42#endif
43#endif
44#endif
45
46#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
47
48#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
49#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
50 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
51#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
52#define CONFIG_SYS_NO_FLASH
53#endif
54
55
56#define CONFIG_BOOKE
57#define CONFIG_E500
58#define CONFIG_E500MC
59#define CONFIG_SYS_BOOK3E_HV
60#define CONFIG_MP
61
62#ifndef CONFIG_SYS_TEXT_BASE
63#define CONFIG_SYS_TEXT_BASE 0xeff40000
64#endif
65
66#ifndef CONFIG_RESET_VECTOR_ADDRESS
67#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
68#endif
69
70#define CONFIG_SYS_FSL_CPC
71#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
72#define CONFIG_FSL_IFC
73#define CONFIG_FSL_CAAM
74#define CONFIG_PCIE1
75#define CONFIG_FSL_PCI_INIT
76#define CONFIG_SYS_PCI_64BIT
77
78#ifndef CONFIG_PPC_B4420
79#define CONFIG_SYS_SRIO
80#define CONFIG_SRIO1
81#define CONFIG_SRIO2
82#define CONFIG_SRIO_PCIE_BOOT_MASTER
83#endif
84
85#define CONFIG_FSL_LAW
86
87
88#define I2C_MUX_PCA_ADDR 0x77
89
90
91#define CONFIG_VSC_CROSSBAR
92#define I2C_CH_DEFAULT 0x8
93#define I2C_CH_VSC3316 0xc
94#define I2C_CH_VSC3308 0xd
95
96#define VSC3316_TX_ADDRESS 0x70
97#define VSC3316_RX_ADDRESS 0x71
98#define VSC3308_TX_ADDRESS 0x02
99#define VSC3308_RX_ADDRESS 0x03
100
101
102#define CONFIG_IDT8T49N222A
103#define I2C_CH_IDT 0x9
104
105#define IDT_SERDES1_ADDRESS 0x6E
106#define IDT_SERDES2_ADDRESS 0x6C
107
108
109#define I2C_MUX_CH_VOL_MONITOR 0xa
110#define I2C_VOL_MONITOR_ADDR 0x40
111#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
112#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
113#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
114
115#define CONFIG_ZM7300
116#define I2C_MUX_CH_DPM 0xa
117#define I2C_DPM_ADDR 0x28
118
119#define CONFIG_ENV_OVERWRITE
120
121#ifdef CONFIG_SYS_NO_FLASH
122#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
123#define CONFIG_ENV_IS_NOWHERE
124#endif
125#else
126#define CONFIG_FLASH_CFI_DRIVER
127#define CONFIG_SYS_FLASH_CFI
128#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
129#endif
130
131#if defined(CONFIG_SPIFLASH)
132#define CONFIG_SYS_EXTRA_ENV_RELOC
133#define CONFIG_ENV_IS_IN_SPI_FLASH
134#define CONFIG_ENV_SPI_BUS 0
135#define CONFIG_ENV_SPI_CS 0
136#define CONFIG_ENV_SPI_MAX_HZ 10000000
137#define CONFIG_ENV_SPI_MODE 0
138#define CONFIG_ENV_SIZE 0x2000
139#define CONFIG_ENV_OFFSET 0x100000
140#define CONFIG_ENV_SECT_SIZE 0x10000
141#elif defined(CONFIG_SDCARD)
142#define CONFIG_SYS_EXTRA_ENV_RELOC
143#define CONFIG_ENV_IS_IN_MMC
144#define CONFIG_SYS_MMC_ENV_DEV 0
145#define CONFIG_ENV_SIZE 0x2000
146#define CONFIG_ENV_OFFSET (512 * 1097)
147#elif defined(CONFIG_NAND)
148#define CONFIG_SYS_EXTRA_ENV_RELOC
149#define CONFIG_ENV_IS_IN_NAND
150#define CONFIG_ENV_SIZE 0x2000
151#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
152#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
153#define CONFIG_ENV_IS_IN_REMOTE
154#define CONFIG_ENV_ADDR 0xffe20000
155#define CONFIG_ENV_SIZE 0x2000
156#elif defined(CONFIG_ENV_IS_NOWHERE)
157#define CONFIG_ENV_SIZE 0x2000
158#else
159#define CONFIG_ENV_IS_IN_FLASH
160#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
161#define CONFIG_ENV_SIZE 0x2000
162#define CONFIG_ENV_SECT_SIZE 0x20000
163#endif
164
165#ifndef __ASSEMBLY__
166unsigned long get_board_sys_clk(void);
167unsigned long get_board_ddr_clk(void);
168#endif
169#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
170#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
171
172
173
174
175#define CONFIG_SYS_CACHE_STASHING
176#define CONFIG_BTB
177#define CONFIG_DDR_ECC
178#ifdef CONFIG_DDR_ECC
179#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
180#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
181#endif
182
183#define CONFIG_ENABLE_36BIT_PHYS
184
185#ifdef CONFIG_PHYS_64BIT
186#define CONFIG_ADDR_MAP
187#define CONFIG_SYS_NUM_ADDR_MAP 64
188#endif
189
190#if 0
191#define CONFIG_POST CONFIG_SYS_POST_MEMORY
192#endif
193#define CONFIG_SYS_MEMTEST_START 0x00200000
194#define CONFIG_SYS_MEMTEST_END 0x00400000
195#define CONFIG_SYS_ALT_MEMTEST
196#define CONFIG_PANIC_HANG
197
198
199
200
201#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
202#define CONFIG_SYS_L3_SIZE 256 << 10
203#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
204#ifdef CONFIG_NAND
205#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
206#endif
207#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
208#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
209#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
210#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
211
212#ifdef CONFIG_PHYS_64BIT
213#define CONFIG_SYS_DCSRBAR 0xf0000000
214#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
215#endif
216
217
218#define CONFIG_ID_EEPROM
219#define CONFIG_SYS_I2C_EEPROM_NXID
220#define CONFIG_SYS_EEPROM_BUS_NUM 0
221#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
222#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
223#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
224#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
225
226
227
228
229#define CONFIG_VERY_BIG_RAM
230#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
231#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
232
233
234#define CONFIG_DIMM_SLOTS_PER_CTLR 1
235#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
236
237#define CONFIG_DDR_SPD
238#define CONFIG_SYS_DDR_RAW_TIMING
239#define CONFIG_SYS_FSL_DDR3
240#ifndef CONFIG_SPL_BUILD
241#define CONFIG_FSL_DDR_INTERACTIVE
242#endif
243
244#define CONFIG_SYS_SPD_BUS_NUM 0
245#define SPD_EEPROM_ADDRESS1 0x51
246#define SPD_EEPROM_ADDRESS2 0x53
247
248#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
249#define CONFIG_SYS_SDRAM_SIZE 2048
250
251
252
253
254#define CONFIG_SYS_FLASH_BASE 0xe0000000
255#ifdef CONFIG_PHYS_64BIT
256#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
257#else
258#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
259#endif
260
261#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
262#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
263 + 0x8000000) | \
264 CSPR_PORT_SIZE_16 | \
265 CSPR_MSEL_NOR | \
266 CSPR_V)
267#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
268#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
269 CSPR_PORT_SIZE_16 | \
270 CSPR_MSEL_NOR | \
271 CSPR_V)
272#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
273
274#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
275#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
276 FTIM0_NOR_TEADC(0x04) | \
277 FTIM0_NOR_TEAHC(0x20))
278#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
279 FTIM1_NOR_TRAD_NOR(0x1A) |\
280 FTIM1_NOR_TSEQRAD_NOR(0x13))
281#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
282 FTIM2_NOR_TCH(0x0E) | \
283 FTIM2_NOR_TWPH(0x0E) | \
284 FTIM2_NOR_TWP(0x1c))
285#define CONFIG_SYS_NOR_FTIM3 0x0
286
287#define CONFIG_SYS_FLASH_QUIET_TEST
288#define CONFIG_FLASH_SHOW_PROGRESS 45
289
290#define CONFIG_SYS_MAX_FLASH_BANKS 2
291#define CONFIG_SYS_MAX_FLASH_SECT 1024
292#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
293#define CONFIG_SYS_FLASH_WRITE_TOUT 500
294
295#define CONFIG_SYS_FLASH_EMPTY_INFO
296#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
297 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
298
299#define CONFIG_FSL_QIXIS
300#define CONFIG_FSL_QIXIS_V2
301#define QIXIS_BASE 0xffdf0000
302#ifdef CONFIG_PHYS_64BIT
303#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
304#else
305#define QIXIS_BASE_PHYS QIXIS_BASE
306#endif
307#define QIXIS_LBMAP_SWITCH 0x01
308#define QIXIS_LBMAP_MASK 0x0f
309#define QIXIS_LBMAP_SHIFT 0
310#define QIXIS_LBMAP_DFLTBANK 0x00
311#define QIXIS_LBMAP_ALTBANK 0x02
312#define QIXIS_RST_CTL_RESET 0x31
313#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
314#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
315#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
316
317#define CONFIG_SYS_CSPR3_EXT (0xf)
318#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
319 | CSPR_PORT_SIZE_8 \
320 | CSPR_MSEL_GPCM \
321 | CSPR_V)
322#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
323#define CONFIG_SYS_CSOR3 0x0
324
325#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
326 FTIM0_GPCM_TEADC(0x0e) | \
327 FTIM0_GPCM_TEAHC(0x0e))
328#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
329 FTIM1_GPCM_TRAD(0x1f))
330#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
331 FTIM2_GPCM_TCH(0x8) | \
332 FTIM2_GPCM_TWP(0x1f))
333#define CONFIG_SYS_CS3_FTIM3 0x0
334
335
336#define CONFIG_NAND_FSL_IFC
337#define CONFIG_SYS_NAND_MAX_ECCPOS 256
338#define CONFIG_SYS_NAND_MAX_OOBFREE 2
339#define CONFIG_SYS_NAND_BASE 0xff800000
340#ifdef CONFIG_PHYS_64BIT
341#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
342#else
343#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
344#endif
345
346#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
347#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
348 | CSPR_PORT_SIZE_8 \
349 | CSPR_MSEL_NAND \
350 | CSPR_V)
351#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
352
353#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
354 | CSOR_NAND_ECC_DEC_EN \
355 | CSOR_NAND_ECC_MODE_4 \
356 | CSOR_NAND_RAL_3 \
357 | CSOR_NAND_PGS_2K \
358 | CSOR_NAND_SPRZ_64 \
359 | CSOR_NAND_PB(64))
360
361#define CONFIG_SYS_NAND_ONFI_DETECTION
362
363
364#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
365 FTIM0_NAND_TWP(0x18) | \
366 FTIM0_NAND_TWCHT(0x07) | \
367 FTIM0_NAND_TWH(0x0a))
368#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
369 FTIM1_NAND_TWBE(0x39) | \
370 FTIM1_NAND_TRR(0x0e) | \
371 FTIM1_NAND_TRP(0x18))
372#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
373 FTIM2_NAND_TREH(0x0a) | \
374 FTIM2_NAND_TWHRE(0x1e))
375#define CONFIG_SYS_NAND_FTIM3 0x0
376
377#define CONFIG_SYS_NAND_DDR_LAW 11
378
379#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
380#define CONFIG_SYS_MAX_NAND_DEVICE 1
381#define CONFIG_CMD_NAND
382
383#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
384
385#if defined(CONFIG_NAND)
386#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
387#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
388#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
389#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
390#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
391#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
392#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
393#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
394#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
395#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
396#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
397#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
398#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
399#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
400#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
401#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
402#else
403#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
404#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
405#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
406#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
407#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
408#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
409#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
410#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
411#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
412#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
413#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
414#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
415#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
416#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
417#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
418#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
419#endif
420#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
421#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
422#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
423#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
424#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
425#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
426#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
427#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
428
429#ifdef CONFIG_SPL_BUILD
430#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
431#else
432#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
433#endif
434
435#if defined(CONFIG_RAMBOOT_PBL)
436#define CONFIG_SYS_RAMBOOT
437#endif
438
439#define CONFIG_BOARD_EARLY_INIT_R
440#define CONFIG_MISC_INIT_R
441
442#define CONFIG_HWCONFIG
443
444
445#define CONFIG_L1_INIT_RAM
446#define CONFIG_SYS_INIT_RAM_LOCK
447#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
448#ifdef CONFIG_PHYS_64BIT
449#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
450#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
451
452#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
453 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
454 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
455#else
456#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000
457#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
458#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
459#endif
460#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
461
462#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
463 GENERATED_GBL_DATA_SIZE)
464#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
465
466#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
467#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
468
469
470
471
472
473#define CONFIG_CONS_INDEX 1
474#define CONFIG_SYS_NS16550_SERIAL
475#define CONFIG_SYS_NS16550_REG_SIZE 1
476#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
477
478#define CONFIG_SYS_BAUDRATE_TABLE \
479 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
480
481#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
482#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
483#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
484#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
485
486
487#define CONFIG_SYS_I2C
488#define CONFIG_SYS_I2C_FSL
489#define CONFIG_SYS_FSL_I2C_SPEED 400000
490#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
491#define CONFIG_SYS_FSL_I2C2_SPEED 400000
492#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
493#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
494#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
495
496
497
498
499#define RTC
500#define CONFIG_RTC_DS3231 1
501#define CONFIG_SYS_I2C_RTC_ADDR 0x68
502
503
504
505
506#ifdef CONFIG_SYS_SRIO
507#ifdef CONFIG_SRIO1
508#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
509#ifdef CONFIG_PHYS_64BIT
510#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
511#else
512#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
513#endif
514#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000
515#endif
516
517#ifdef CONFIG_SRIO2
518#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
519#ifdef CONFIG_PHYS_64BIT
520#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
521#else
522#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
523#endif
524#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000
525#endif
526#endif
527
528
529
530
531
532#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
533#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
534#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
535#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
536
537
538
539
540#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
541#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
542#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
543
544
545#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
546#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
547
548
549
550
551#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
552#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
553#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
554 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
555#endif
556
557
558
559
560#define CONFIG_SF_DEFAULT_SPEED 10000000
561#define CONFIG_SF_DEFAULT_MODE 0
562
563
564
565
566#ifdef CONFIG_PHYS_64BIT
567#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
568#else
569#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
570#endif
571
572
573
574
575
576
577
578#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
579#ifdef CONFIG_PHYS_64BIT
580#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
581#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
582#else
583#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
584#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
585#endif
586#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
587#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
588#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
589#ifdef CONFIG_PHYS_64BIT
590#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
591#else
592#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
593#endif
594#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
595
596
597#ifndef CONFIG_NOBQFMAN
598#define CONFIG_SYS_DPAA_QBMAN
599#define CONFIG_SYS_BMAN_NUM_PORTALS 25
600#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
601#ifdef CONFIG_PHYS_64BIT
602#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
603#else
604#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
605#endif
606#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
607#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
608#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
609#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
610#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
611#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
612 CONFIG_SYS_BMAN_CENA_SIZE)
613#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
614#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
615#define CONFIG_SYS_QMAN_NUM_PORTALS 25
616#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
617#ifdef CONFIG_PHYS_64BIT
618#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
619#else
620#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
621#endif
622#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
623#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
624#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
625#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
626#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
627#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
628 CONFIG_SYS_QMAN_CENA_SIZE)
629#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
630#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
631
632#define CONFIG_SYS_DPAA_FMAN
633
634#define CONFIG_SYS_DPAA_RMAN
635
636
637#if defined(CONFIG_SPIFLASH)
638
639
640
641
642#define CONFIG_SYS_QE_FW_IN_SPIFLASH
643#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
644#elif defined(CONFIG_SDCARD)
645
646
647
648
649
650#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
651#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
652#elif defined(CONFIG_NAND)
653#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
654#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
655#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
656
657
658
659
660
661
662
663#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
664#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
665#else
666#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
667#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
668#endif
669#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
670#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
671#endif
672
673#ifdef CONFIG_SYS_DPAA_FMAN
674#define CONFIG_FMAN_ENET
675#define CONFIG_PHYLIB_10G
676#define CONFIG_PHY_VITESSE
677#define CONFIG_PHY_TERANETICS
678#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
679#define SGMII_CARD_PORT2_PHY_ADDR 0x10
680#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
681#define SGMII_CARD_PORT4_PHY_ADDR 0x11
682#endif
683
684#ifdef CONFIG_PCI
685#define CONFIG_PCI_INDIRECT_BRIDGE
686
687#define CONFIG_PCI_SCAN_SHOW
688#define CONFIG_DOS_PARTITION
689#endif
690
691#ifdef CONFIG_FMAN_ENET
692#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
693#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
694
695
696#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7
697#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6
698
699#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
700#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
701#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
702#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
703
704#define CONFIG_MII
705#define CONFIG_ETHPRIME "FM1@DTSEC1"
706#define CONFIG_PHY_GIGE
707#endif
708
709#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
710
711
712
713
714#define CONFIG_LOADS_ECHO
715#define CONFIG_SYS_LOADS_BAUD_CHANGE
716
717
718
719
720#define CONFIG_CMD_DATE
721#define CONFIG_CMD_EEPROM
722#define CONFIG_CMD_ERRATA
723#define CONFIG_CMD_IRQ
724#define CONFIG_CMD_REGINFO
725
726#ifdef CONFIG_PCI
727#define CONFIG_CMD_PCI
728#endif
729
730
731#ifdef CONFIG_FSL_CAAM
732#define CONFIG_CMD_HASH
733#define CONFIG_SHA_HW_ACCEL
734#endif
735
736
737
738
739#define CONFIG_HAS_FSL_DR_USB
740
741#ifdef CONFIG_HAS_FSL_DR_USB
742#define CONFIG_USB_EHCI
743
744#ifdef CONFIG_USB_EHCI
745#define CONFIG_USB_EHCI_FSL
746#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
747#endif
748#endif
749
750
751
752
753#define CONFIG_SYS_LONGHELP
754#define CONFIG_CMDLINE_EDITING
755#define CONFIG_AUTO_COMPLETE
756#define CONFIG_SYS_LOAD_ADDR 0x2000000
757#ifdef CONFIG_CMD_KGDB
758#define CONFIG_SYS_CBSIZE 1024
759#else
760#define CONFIG_SYS_CBSIZE 256
761#endif
762#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
763#define CONFIG_SYS_MAXARGS 16
764#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
765
766
767
768
769
770
771#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
772#define CONFIG_SYS_BOOTM_LEN (64 << 20)
773
774#ifdef CONFIG_CMD_KGDB
775#define CONFIG_KGDB_BAUDRATE 230400
776#endif
777
778
779
780
781#define CONFIG_ROOTPATH "/opt/nfsroot"
782#define CONFIG_BOOTFILE "uImage"
783#define CONFIG_UBOOTPATH "u-boot.bin"
784
785
786#define CONFIG_LOADADDR 1000000
787
788
789#define CONFIG_BAUDRATE 115200
790
791#define __USB_PHY_TYPE ulpi
792
793#ifdef CONFIG_PPC_B4860
794#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
795 "bank_intlv=cs0_cs1;" \
796 "en_cpc:cpc2;"
797#else
798#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
799#endif
800
801#define CONFIG_EXTRA_ENV_SETTINGS \
802 HWCONFIG \
803 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
804 "netdev=eth0\0" \
805 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
806 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
807 "tftpflash=tftpboot $loadaddr $uboot && " \
808 "protect off $ubootaddr +$filesize && " \
809 "erase $ubootaddr +$filesize && " \
810 "cp.b $loadaddr $ubootaddr $filesize && " \
811 "protect on $ubootaddr +$filesize && " \
812 "cmp.b $loadaddr $ubootaddr $filesize\0" \
813 "consoledev=ttyS0\0" \
814 "ramdiskaddr=2000000\0" \
815 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
816 "fdtaddr=1e00000\0" \
817 "fdtfile=b4860qds/b4860qds.dtb\0" \
818 "bdev=sda3\0"
819
820
821
822#define CONFIG_PROOF_POINTS \
823 "setenv bootargs root=/dev/$bdev rw " \
824 "console=$consoledev,$baudrate $othbootargs;" \
825 "cpu 1 release 0x29000000 - - -;" \
826 "cpu 2 release 0x29000000 - - -;" \
827 "cpu 3 release 0x29000000 - - -;" \
828 "cpu 4 release 0x29000000 - - -;" \
829 "cpu 5 release 0x29000000 - - -;" \
830 "cpu 6 release 0x29000000 - - -;" \
831 "cpu 7 release 0x29000000 - - -;" \
832 "go 0x29000000"
833
834#define CONFIG_HVBOOT \
835 "setenv bootargs config-addr=0x60000000; " \
836 "bootm 0x01000000 - 0x00f00000"
837
838#define CONFIG_ALU \
839 "setenv bootargs root=/dev/$bdev rw " \
840 "console=$consoledev,$baudrate $othbootargs;" \
841 "cpu 1 release 0x01000000 - - -;" \
842 "cpu 2 release 0x01000000 - - -;" \
843 "cpu 3 release 0x01000000 - - -;" \
844 "cpu 4 release 0x01000000 - - -;" \
845 "cpu 5 release 0x01000000 - - -;" \
846 "cpu 6 release 0x01000000 - - -;" \
847 "cpu 7 release 0x01000000 - - -;" \
848 "go 0x01000000"
849
850#define CONFIG_LINUX \
851 "setenv bootargs root=/dev/ram rw " \
852 "console=$consoledev,$baudrate $othbootargs;" \
853 "setenv ramdiskaddr 0x02000000;" \
854 "setenv fdtaddr 0x01e00000;" \
855 "setenv loadaddr 0x1000000;" \
856 "bootm $loadaddr $ramdiskaddr $fdtaddr"
857
858#define CONFIG_HDBOOT \
859 "setenv bootargs root=/dev/$bdev rw " \
860 "console=$consoledev,$baudrate $othbootargs;" \
861 "tftp $loadaddr $bootfile;" \
862 "tftp $fdtaddr $fdtfile;" \
863 "bootm $loadaddr - $fdtaddr"
864
865#define CONFIG_NFSBOOTCOMMAND \
866 "setenv bootargs root=/dev/nfs rw " \
867 "nfsroot=$serverip:$rootpath " \
868 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
869 "console=$consoledev,$baudrate $othbootargs;" \
870 "tftp $loadaddr $bootfile;" \
871 "tftp $fdtaddr $fdtfile;" \
872 "bootm $loadaddr - $fdtaddr"
873
874#define CONFIG_RAMBOOTCOMMAND \
875 "setenv bootargs root=/dev/ram rw " \
876 "console=$consoledev,$baudrate $othbootargs;" \
877 "tftp $ramdiskaddr $ramdiskfile;" \
878 "tftp $loadaddr $bootfile;" \
879 "tftp $fdtaddr $fdtfile;" \
880 "bootm $loadaddr $ramdiskaddr $fdtaddr"
881
882#define CONFIG_BOOTCOMMAND CONFIG_LINUX
883
884#include <asm/fsl_secure_boot.h>
885
886#endif
887