1/* 2 * Configuation settings for the esd TASREG board. 3 * 4 * (C) Copyright 2004 5 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * board/config.h - configuration options, board specific 12 */ 13 14#ifndef _M5249EVB_H 15#define _M5249EVB_H 16 17/* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21#define CONFIG_MCFTMR 22 23#define CONFIG_MCFUART 24#define CONFIG_SYS_UART_PORT (0) 25#define CONFIG_BAUDRATE 115200 26 27#undef CONFIG_WATCHDOG 28 29#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ 30 31/* 32 * BOOTP options 33 */ 34#undef CONFIG_BOOTP_BOOTFILESIZE 35#undef CONFIG_BOOTP_BOOTPATH 36#undef CONFIG_BOOTP_GATEWAY 37#undef CONFIG_BOOTP_HOSTNAME 38 39/* 40 * Command line configuration. 41 */ 42 43#define CONFIG_SYS_LONGHELP /* undef to save memory */ 44 45#if defined(CONFIG_CMD_KGDB) 46#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 47#else 48#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 49#endif 50#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 51#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 52#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 53 54#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 55#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 56#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 57 58#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ 59 60#define CONFIG_SYS_MEMTEST_START 0x400 61#define CONFIG_SYS_MEMTEST_END 0x380000 62 63/* 64 * Clock configuration: enable only one of the following options 65 */ 66 67#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 68#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ 69#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ 70 71/* 72 * Low Level Configuration Settings 73 * (address mappings, register initial values, etc.) 74 * You should know what you are doing if you make changes here. 75 */ 76 77#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 78#define CONFIG_SYS_MBAR2 0x80000000 79 80/*----------------------------------------------------------------------- 81 * Definitions for initial stack pointer and data area (in DPRAM) 82 */ 83#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 84#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 85#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 86#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 87 88#define CONFIG_ENV_IS_IN_FLASH 1 89 90#define LDS_BOARD_TEXT \ 91 . = DEFINED(env_offset) ? env_offset : .; \ 92 common/env_embedded.o (.text); 93 94#define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ 95#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 96#define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ 97 98/*----------------------------------------------------------------------- 99 * Start addresses for the final memory configuration 100 * (Set up by the startup code) 101 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 102 */ 103#define CONFIG_SYS_SDRAM_BASE 0x00000000 104#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 105#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 106 107#if 0 /* test-only */ 108#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ 109#endif 110 111#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 112 113#define CONFIG_SYS_MONITOR_LEN 0x20000 114#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ 115#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 116 117/* 118 * For booting Linux, the board info and command line data 119 * have to be in the first 8 MB of memory, since this is 120 * the maximum mapped by the Linux kernel during initialization ?? 121 */ 122#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 123 124/*----------------------------------------------------------------------- 125 * FLASH organization 126 */ 127#define CONFIG_SYS_FLASH_CFI 128#ifdef CONFIG_SYS_FLASH_CFI 129 130# define CONFIG_FLASH_CFI_DRIVER 1 131# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 132# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 133# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 134# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 135# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 136# define CONFIG_SYS_FLASH_CHECKSUM 137# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 138#endif 139 140/*----------------------------------------------------------------------- 141 * Cache Configuration 142 */ 143#define CONFIG_SYS_CACHELINE_SIZE 16 144 145#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 146 CONFIG_SYS_INIT_RAM_SIZE - 8) 147#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 148 CONFIG_SYS_INIT_RAM_SIZE - 4) 149#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 150#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 151 CF_ADDRMASK(2) | \ 152 CF_ACR_EN | CF_ACR_SM_ALL) 153#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 154 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 155 CF_ACR_EN | CF_ACR_SM_ALL) 156#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 157 CF_CACR_DBWE) 158 159/*----------------------------------------------------------------------- 160 * Memory bank definitions 161 */ 162 163/* CS0 - AMD Flash, address 0xffc00000 */ 164#define CONFIG_SYS_CS0_BASE 0xffe00000 165#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ 166/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ 167#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ 168 169/* CS1 - FPGA, address 0xe0000000 */ 170#define CONFIG_SYS_CS1_BASE 0xe0000000 171#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ 172#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ 173 174/*----------------------------------------------------------------------- 175 * Port configuration 176 */ 177#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 178#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ 179#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 180#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 181#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 182#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 183#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 184 185#endif /* M5249 */ 186